{"title":"2.5 mW/ch, 50 Mcps, 10个模拟通道,具有9.71 ps-RMS时序分辨率的自适应偏置读出前端IC,用于90 nm CMOS中的单光子飞行时间PET应用","authors":"H. Cruz, Hong-Yi Huang, Shueen-Yu Lee, C. Luo","doi":"10.1109/VLSI-DAT.2015.7114501","DOIUrl":null,"url":null,"abstract":"A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS\",\"authors\":\"H. Cruz, Hong-Yi Huang, Shueen-Yu Lee, C. Luo\",\"doi\":\"10.1109/VLSI-DAT.2015.7114501\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.\",\"PeriodicalId\":369130,\"journal\":{\"name\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT.2015.7114501\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114501","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS
A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.