{"title":"一个统一的多角多模式静态时序分析引擎","authors":"Jing-Jia Nian, Shihgeng Tsai, Chung-Yang Huang","doi":"10.1109/ASPDAC.2010.5419804","DOIUrl":null,"url":null,"abstract":"In this paper, we proposed a unified multi-corner multi-mode (MCMM) static timing analysis (STA) engine that can efficiently compute the worst-case delay of the process corners in various very large scaled circuits. Our key contributions include: (1) a seamless integration of the path-and parameter-based branch-and-bound algorithms so that the engine is very robust for different kinds of circuits, (2) an improved search space pruning technique, (3) a simple yet efficient critical path delay bound for the initial search space pruning. Our experimental results show that our engine can significantly outperform the prior MCMM STA approaches in various benchmark circuits with different number of process parameters.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A unified Multi-Corner Multi-Mode static timing analysis engine\",\"authors\":\"Jing-Jia Nian, Shihgeng Tsai, Chung-Yang Huang\",\"doi\":\"10.1109/ASPDAC.2010.5419804\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we proposed a unified multi-corner multi-mode (MCMM) static timing analysis (STA) engine that can efficiently compute the worst-case delay of the process corners in various very large scaled circuits. Our key contributions include: (1) a seamless integration of the path-and parameter-based branch-and-bound algorithms so that the engine is very robust for different kinds of circuits, (2) an improved search space pruning technique, (3) a simple yet efficient critical path delay bound for the initial search space pruning. Our experimental results show that our engine can significantly outperform the prior MCMM STA approaches in various benchmark circuits with different number of process parameters.\",\"PeriodicalId\":152569,\"journal\":{\"name\":\"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-01-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.2010.5419804\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2010.5419804","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A unified Multi-Corner Multi-Mode static timing analysis engine
In this paper, we proposed a unified multi-corner multi-mode (MCMM) static timing analysis (STA) engine that can efficiently compute the worst-case delay of the process corners in various very large scaled circuits. Our key contributions include: (1) a seamless integration of the path-and parameter-based branch-and-bound algorithms so that the engine is very robust for different kinds of circuits, (2) an improved search space pruning technique, (3) a simple yet efficient critical path delay bound for the initial search space pruning. Our experimental results show that our engine can significantly outperform the prior MCMM STA approaches in various benchmark circuits with different number of process parameters.