垂直堆叠纳米片技术中高压器件的性能与可靠性协同设计

2022 IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2022-12-11 DOI:10.1109/ICEE56203.2022.10118336

J. Jatin, M. Monishmurali, S. K. Gautam, M. Shrivastava

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引用次数: 0

摘要

在这项工作中，首次在片上系统(SoC)集成的背景下研究了基于漏极扩展垂直堆叠纳米片的高压器件。通过3D TCAD过程模拟，详细阐述了器件性能和ESD可靠性的物理见解。最后，对纳米片技术中高压器件的性能和可靠性协同设计准则进行了全面的讨论。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Performance and Reliability Co-Design of HV devices in Vertically Stacked Nanosheet Technology

In this work, for the first time, Drain-Extended vertically stacked Nanosheet-based HV device has been studied in the context of System-On-Chip (SoC) integration. Physical insights into the device performance and ESD reliability are elaborated using 3D TCAD process simulations. Finally, the performance and reliability co-design guidelines related to HV devices in Nanosheets technology have been discussed comprehensively.

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2022 IEEE International Conference on Emerging Electronics (ICEE)

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