用于集成ADSL模拟前端的嵌入式数字自适应偏置算法的0.5/spl mu/m CMOS低失真低功耗线路驱动器

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992243

M. Ingels, S. Bojja, P. Wouters

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引用次数: 2

摘要

一个5V 0.5/spl mu/m的CMOS线路驱动器，在12.5/spl ω /负载下，在4V峰对峰差分输出摆幅下，在ADSL上行频段失真<-65dB。静态电流通过专用算法进行数字控制，该算法可校正偏移和过程变化。驱动程序集成在一个完整的ADSL CPE模拟前端中。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 0.5/spl mu/m CMOS low-distortion low-power line driver with embedded digital adaptive bias algorithm for integrated ADSL analog front-ends

A 5V 0.5/spl mu/m CMOS line driver has distortion <-65dB in the ADSL upstream band for a 4V peak-to-peak differential output swing on a 12.5/spl Omega/ load. The quiescent current is controlled digitally with a dedicated algorithm that corrects for offsets and process variations. The driver is integrated in a complete ADSL CPE analog front-end.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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