{"title":"提高晶圆级可靠性表征的速度:新方法和限制","authors":"B. Bittel, S. Vadlamani, S. Ramey, S. Padiyar","doi":"10.1109/IIRW.2016.7904909","DOIUrl":null,"url":null,"abstract":"Tremendous amounts of wafer level reliability testing is required to support transistor technology development efforts. Conventional testing takes considerable time which severely limits reliability organizations. We present two approaches that help increase data velocity for wafer level reliability measurements and discuss their current limitations.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Increasing velocity of wafer level reliability characterization: Novel approaches and limitations\",\"authors\":\"B. Bittel, S. Vadlamani, S. Ramey, S. Padiyar\",\"doi\":\"10.1109/IIRW.2016.7904909\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Tremendous amounts of wafer level reliability testing is required to support transistor technology development efforts. Conventional testing takes considerable time which severely limits reliability organizations. We present two approaches that help increase data velocity for wafer level reliability measurements and discuss their current limitations.\",\"PeriodicalId\":436183,\"journal\":{\"name\":\"2016 IEEE International Integrated Reliability Workshop (IIRW)\",\"volume\":\"110 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Integrated Reliability Workshop (IIRW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2016.7904909\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Integrated Reliability Workshop (IIRW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2016.7904909","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Increasing velocity of wafer level reliability characterization: Novel approaches and limitations
Tremendous amounts of wafer level reliability testing is required to support transistor technology development efforts. Conventional testing takes considerable time which severely limits reliability organizations. We present two approaches that help increase data velocity for wafer level reliability measurements and discuss their current limitations.