Pub Date : 2016-10-09DOI: 10.1109/IIRW.2016.7904908
D. Nouguier, C. Ndiaye, G. Ghibaudo, X. Federspiel, M. Rafik, D. Roy
In this paper, we propose a qualitative analysis of NBTI recoverable components measured on pFET devices issued from various ST Microelectronics (28nm FDSOI technology and 40nm SION or Bulk) technologies. NBTI degradation and recovery resulting from DC stress are measured at µs time scale. We observed similarities between temperature and Vgrecovery dependencies on NBTI relaxation of SiON and FDSOI technologies. Then, we discuss the nature of one defect type responsible for the NBTI at early stage of relaxation.
{"title":"Improved analysis of NBTI relaxation behavior based on fast I–V measurement","authors":"D. Nouguier, C. Ndiaye, G. Ghibaudo, X. Federspiel, M. Rafik, D. Roy","doi":"10.1109/IIRW.2016.7904908","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904908","url":null,"abstract":"In this paper, we propose a qualitative analysis of NBTI recoverable components measured on pFET devices issued from various ST Microelectronics (28nm FDSOI technology and 40nm SION or Bulk) technologies. NBTI degradation and recovery resulting from DC stress are measured at µs time scale. We observed similarities between temperature and Vgrecovery dependencies on NBTI relaxation of SiON and FDSOI technologies. Then, we discuss the nature of one defect type responsible for the NBTI at early stage of relaxation.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133955519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-09DOI: 10.1109/IIRW.2016.7904903
Jiahui Wang, C. Salm, E. Houwman, M. Nguyen, J. Schmitz
This paper presents a reliability study on unpackaged metal-PZT-metal capacitors. Both ramped voltage stress (RVS) and time dependent dielectric breakdown (TDDB) measurements show that environmental humidity dramatically worsens the PZT reliability. Visible breakdown spots on the surface of PZT capacitors are studied in detail. The measurement results indicate that both reversible and irreversible PZT degradation/breakdown happen during TDDB. The dependence of time to breakdown on polarity of applied voltage is argued to relate to the crystal structure of PZT and the stack of the PZT capacitor.
{"title":"Humidity and polarity influence on MIM PZT capacitor degradation and breakdown","authors":"Jiahui Wang, C. Salm, E. Houwman, M. Nguyen, J. Schmitz","doi":"10.1109/IIRW.2016.7904903","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904903","url":null,"abstract":"This paper presents a reliability study on unpackaged metal-PZT-metal capacitors. Both ramped voltage stress (RVS) and time dependent dielectric breakdown (TDDB) measurements show that environmental humidity dramatically worsens the PZT reliability. Visible breakdown spots on the surface of PZT capacitors are studied in detail. The measurement results indicate that both reversible and irreversible PZT degradation/breakdown happen during TDDB. The dependence of time to breakdown on polarity of applied voltage is argued to relate to the crystal structure of PZT and the stack of the PZT capacitor.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121196456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904897
J. Hao, D. Hahn
This paper reports two methods to reduce HC degradation in high voltage LNDMOS device without sacrificing the device breakdown voltage and Rdson in BCD technology. The first method modifies the front end process by forming a thick oxide in drift region-I. The process modification is achieved with a simple layout change in BCD technology. Experimental data shows this modification has significantly improved HC degradation in the LNDMOS. The second method modifies back end processes by adding a unique SiN barrier layer which we believe reduces plasma induced damage on the LNDMOS. We demonstrate the barrier layer can improve device hot carrier performance in the LNDMOS.
{"title":"Reduction of hot carrier degradation in high voltage n-channel LDMOS BCD (Bipolar-CMOS-DMOS) technology","authors":"J. Hao, D. Hahn","doi":"10.1109/IIRW.2016.7904897","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904897","url":null,"abstract":"This paper reports two methods to reduce HC degradation in high voltage LNDMOS device without sacrificing the device breakdown voltage and Rdson in BCD technology. The first method modifies the front end process by forming a thick oxide in drift region-I. The process modification is achieved with a simple layout change in BCD technology. Experimental data shows this modification has significantly improved HC degradation in the LNDMOS. The second method modifies back end processes by adding a unique SiN barrier layer which we believe reduces plasma induced damage on the LNDMOS. We demonstrate the barrier layer can improve device hot carrier performance in the LNDMOS.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128295202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904889
Y. Huang, L. Hsu, W. Chou, M. Hsieh, K. Shih, N. Tseng, R. B. Pittu, W. Wang, Y. Lee
One of the major purposes of characterizing discrete device reliability is to provide reasonable margin during design phase. Prevention is always better than a cure from risk control and cost management point of view. Over the last decade, foundry has been asked to provide aging aware IP and cell library to reduce customers' product development cycle. Though these libraries were well characterized but their aging behaviors were left to designers' own judgments. To integrate aging effect into static timing analysis (STA) either for synthesis or post-simulation, one needs a fairly accurate SPICE aging model which covers AC stress [1] and gate level (or standard cell level) timing shift. This demands Si-to-Simulation comparisons which will be addressed in this paper.
{"title":"AC stress and standard cell aging characterization to enhance reliability coverage of logic circuits","authors":"Y. Huang, L. Hsu, W. Chou, M. Hsieh, K. Shih, N. Tseng, R. B. Pittu, W. Wang, Y. Lee","doi":"10.1109/IIRW.2016.7904889","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904889","url":null,"abstract":"One of the major purposes of characterizing discrete device reliability is to provide reasonable margin during design phase. Prevention is always better than a cure from risk control and cost management point of view. Over the last decade, foundry has been asked to provide aging aware IP and cell library to reduce customers' product development cycle. Though these libraries were well characterized but their aging behaviors were left to designers' own judgments. To integrate aging effect into static timing analysis (STA) either for synthesis or post-simulation, one needs a fairly accurate SPICE aging model which covers AC stress [1] and gate level (or standard cell level) timing shift. This demands Si-to-Simulation comparisons which will be addressed in this paper.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121118245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904899
L. Sheng
A practical model of physically interpreting electrical responses was proposed to quantify the enhancement effects of local electrical fields along the complex poly-oxide-poly interfaces. In revealing the unique test polarity dependence of breakdown voltage and IV characteristics, the excellent agreement between TCAD simulations and measurements have fully validated the existence of locally enhanced fields. As a result, the reliability pitfalls, i.e., the artificially alternated model-fitting parameters, have been manifested for the first time in assessing the TDDB lifetimes under locally enhanced electrical fields due to the interfacial roughness.
{"title":"A physical manifestation of interfacial roughness pitfalls in assessing dielectric TDDB lifetimes","authors":"L. Sheng","doi":"10.1109/IIRW.2016.7904899","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904899","url":null,"abstract":"A practical model of physically interpreting electrical responses was proposed to quantify the enhancement effects of local electrical fields along the complex poly-oxide-poly interfaces. In revealing the unique test polarity dependence of breakdown voltage and IV characteristics, the excellent agreement between TCAD simulations and measurements have fully validated the existence of locally enhanced fields. As a result, the reliability pitfalls, i.e., the artificially alternated model-fitting parameters, have been manifested for the first time in assessing the TDDB lifetimes under locally enhanced electrical fields due to the interfacial roughness.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121165315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904906
N. Mahmud, Avyaya J. Narasimham, J. Lloyd
1/f Noise levels in Hafnium Oxide based bipolar ReRAM devices are studied using an ac + dc measurement technique. Preliminary results support the idea that the current conducts through a low resistive metal rich filament at low resistance state (LRS) and the current at high resistance state (HRS) is a trap-assisted current. The technique used here, allows to estimate the noise levels around 1 Hz.
{"title":"1/f Noise analysis of Hafnium Oxide based ReRAM devices using ac + dc measurement technique","authors":"N. Mahmud, Avyaya J. Narasimham, J. Lloyd","doi":"10.1109/IIRW.2016.7904906","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904906","url":null,"abstract":"1/f Noise levels in Hafnium Oxide based bipolar ReRAM devices are studied using an ac + dc measurement technique. Preliminary results support the idea that the current conducts through a low resistive metal rich filament at low resistance state (LRS) and the current at high resistance state (HRS) is a trap-assisted current. The technique used here, allows to estimate the noise levels around 1 Hz.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126441020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904891
F. Puglisi
In this work, we report a detailed discussion on the techniques and the requirements needed to enable Random Telegraph Noise (RTN) analysis as a tool to investigate device reliability. Starting with the understanding of the RTN signal properties, a set of best practices to perform measurements and data analysis is established to guarantee reliable results and a correct ensuing physical interpretation. It will be shown that combining dedicated and careful experiments with refined data analysis and comprehensive physics simulations is hence required to enable RTN analysis as a safe and innovative investigation tool for electron devices. The effectiveness of RTN analysis as an investigation tool is demonstrated on both FinFET and resistive memory devices: the parameters of RTN as observed in the experiments performed on FinFETs allow understanding the details of the defects generation during stress in such devices; RTN analysis on RRAM allows understanding the physical origin of RTN in these devices and to estimate the physical properties of defects involved in the phenomenon.
{"title":"Random Telegraph Noise analysis as a tool to link physical device features to electrical reliability in nanoscale devices","authors":"F. Puglisi","doi":"10.1109/IIRW.2016.7904891","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904891","url":null,"abstract":"In this work, we report a detailed discussion on the techniques and the requirements needed to enable Random Telegraph Noise (RTN) analysis as a tool to investigate device reliability. Starting with the understanding of the RTN signal properties, a set of best practices to perform measurements and data analysis is established to guarantee reliable results and a correct ensuing physical interpretation. It will be shown that combining dedicated and careful experiments with refined data analysis and comprehensive physics simulations is hence required to enable RTN analysis as a safe and innovative investigation tool for electron devices. The effectiveness of RTN analysis as an investigation tool is demonstrated on both FinFET and resistive memory devices: the parameters of RTN as observed in the experiments performed on FinFETs allow understanding the details of the defects generation during stress in such devices; RTN analysis on RRAM allows understanding the physical origin of RTN in these devices and to estimate the physical properties of defects involved in the phenomenon.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122398111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904901
A. Basavalingappa, M. Shen, J. Lloyd
Copper in spite of being face centered cubic crystal has significant mechanical anisotropy. The elastic constants of copper vary considerably for different crystallographic orientations. Typically, the copper metal conductor lines in integrated circuits are polycrystalline in nature. The polycrystalline microstructure is known to impact the reliability and is yet to be thoroughly understood. In this work we used Voronoi tessellation to model the polycrystalline microstructure for the copper metal lines in test structures. Each of the grains was then assigned an orientation with distinct probabilistic texture with (111) as the preferred orientation and corresponding anisotropic elastic constants based on the assigned orientation. By subjecting the test structure through a thermal stress, we observed over 70% variation in hydrostatic stresses along the grain boundaries depending on the orientation, dimensions, surroundings, and location of the grains. This may introduce new weak points within the metal interconnects leading to failure. Hence, inclusion of microstructures and corresponding anisotropic properties for copper grains is crucial to conduct a realistic study of both the stress voiding and electromigration phenomena, especially at smaller nodes where the anisotropic effects are significant.
{"title":"Effect of texture and elastic anisotropy of copper microstructure on reliability","authors":"A. Basavalingappa, M. Shen, J. Lloyd","doi":"10.1109/IIRW.2016.7904901","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904901","url":null,"abstract":"Copper in spite of being face centered cubic crystal has significant mechanical anisotropy. The elastic constants of copper vary considerably for different crystallographic orientations. Typically, the copper metal conductor lines in integrated circuits are polycrystalline in nature. The polycrystalline microstructure is known to impact the reliability and is yet to be thoroughly understood. In this work we used Voronoi tessellation to model the polycrystalline microstructure for the copper metal lines in test structures. Each of the grains was then assigned an orientation with distinct probabilistic texture with (111) as the preferred orientation and corresponding anisotropic elastic constants based on the assigned orientation. By subjecting the test structure through a thermal stress, we observed over 70% variation in hydrostatic stresses along the grain boundaries depending on the orientation, dimensions, surroundings, and location of the grains. This may introduce new weak points within the metal interconnects leading to failure. Hence, inclusion of microstructures and corresponding anisotropic properties for copper grains is crucial to conduct a realistic study of both the stress voiding and electromigration phenomena, especially at smaller nodes where the anisotropic effects are significant.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117235120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904898
Z. Chbili, A. Kerber
Self-heating is a growing concern for thin-body devices. In this paper, we discuss the impact of self-heating on TDDB using uniform and non-uniform gate dielectric stress. We show lifetime reduction with increasing drain voltages consistent with elevated temperature stress. It is also shown that the power law dependence to gate voltage is preserved at different drain voltages. Due to limited self-heating during nominal device operation TDDB lifetime is not reduced for CMOS circuits.
{"title":"Self-heating impact on TDDB in bulk FinFET devices: Uniform vs Non-uniform Stress","authors":"Z. Chbili, A. Kerber","doi":"10.1109/IIRW.2016.7904898","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904898","url":null,"abstract":"Self-heating is a growing concern for thin-body devices. In this paper, we discuss the impact of self-heating on TDDB using uniform and non-uniform gate dielectric stress. We show lifetime reduction with increasing drain voltages consistent with elevated temperature stress. It is also shown that the power law dependence to gate voltage is preserved at different drain voltages. Due to limited self-heating during nominal device operation TDDB lifetime is not reduced for CMOS circuits.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129881098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904912
R. J. Waskiewicz, Michael J. Mutch, P. Lenahan, S. King
We investigate leakage currents in a-SiOC:H thin films with electrically detected magnetic resonance (EDMR) and new zero field magnetoresistance measurements. We substantially change leakage currents by subjecting the dielectrics to 60Co gamma irradiation. Our results strongly suggest the potential of a very simple measurement, near zero field magnetoresistance, as a reliability physics tool in the investigation of transport mechanisms in these materials.
{"title":"Radiation induced leakage currents in dense and porous low-k dielectrics","authors":"R. J. Waskiewicz, Michael J. Mutch, P. Lenahan, S. King","doi":"10.1109/IIRW.2016.7904912","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904912","url":null,"abstract":"We investigate leakage currents in a-SiOC:H thin films with electrically detected magnetic resonance (EDMR) and new zero field magnetoresistance measurements. We substantially change leakage currents by subjecting the dielectrics to 60Co gamma irradiation. Our results strongly suggest the potential of a very simple measurement, near zero field magnetoresistance, as a reliability physics tool in the investigation of transport mechanisms in these materials.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125664552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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