A submicron VLSI memory with a 4b-at-a-time built-in ECC circuit

THIS PAPER WILL REPORT ON AN experimental 1Mb dynamic memory, utilizing a 4 bit-at-a-time Error Checking and Correcting (ECC) circuit, and a high-sensitivity distributed sense circuit. A 1Mb DRAM using a 2 0 ~ 2 cell was designed and fabricated with an 0 . 8 ~ CMOS process. An on-chip ECC is essential for megabit level dynamic RAMs to reduce an alpha particle-induced soft error rate. For practical use, a small-sized ECC circuit applicable to multi-bit devices is required instead of one applicable to single-bit devices'. Figure 1 shows the principle of the proposed 4b-at-a-time ECC using a bi-directional parity code. An HV-parity cell is connected with each word line as well as Hand V-parity cells to check all of the data in the memory and parity cells. Each data in the HI-, HZ-, Vi-, and V2-groups are selected to carry out four types of parity checking. By combining the parity-checked result of each Hgroup data, with that of each V-group data, four correcting signals are acquired simultaneously. In applying this 4b-at-a-time ECC to megabit level RAMs, selector design is most important in reducing its size. The best configuration of a selector is obtained by minimizing the number of selector lines, as shown in Figure 2. Parity check circuits are arranged on the upper and lower sides of the selector. The II1-group data are transferred upward to check the data in the upper half of the memory cell array. The Vi-group data, however, are transferred upward and downward to check the data in the upper-left and lower-left quarters of the array. With such a configuration, the selector size for this 4b-at-a-time ECC is reduced so that it is as small as that required for a single bit ECC. In addition, since the ECC incorporates a self-checking function, the size of a parity cell can be made the same as that of the memory cell, maintaining the reduced soft error rate. As a result, the ECC circuit occupied about 12% of the entire chip area. To overcome the problem of a small storage node capacitance (CS) in megabit level dynamic RAMs, it is necessary to realize a high-sensitivity sense circuit. The distributed sense circuit proposed achieves this result by reducing the effective bit-line capacitance (CB). As shown in Figure 3, the sense circuit is composed of a main amplifier and distributively arranged preamplifiers, each of which has an address controlled switch. In pre-sensing, since all the switches are turned off, the ratio of CB/CS becomes smaller and the pre-sensed signal can be obtained by the selected preamplifier. After pre-sensing, all of the switches are turned on to transfer the pre-sensed signal to the main amplifier. After this operation, a high-speed sensing is performed in cooperation with the main amplifier and all of the preamplifiers combined. Since the pre-sensed signal is transferred through __