An Ultra-low-Power Quadrature PLL in 130nm CMOS for Impulse Radio Receivers

This paper discusses an architecture for an integrated ultra-low power impulse radio receiver for low data rate applications such as biomedical sensor networks. Choosing a proper system architecture allows to implement a receiver with relaxed specifications for the typical building blocks which results in a low-power implementation. Furthermore a design in 130 nm CMOS of a fully integrated ultra-low power PLL, a critical block of such receivers, is presented. The PLL serves a double purpose. It acts as the master clock generator for the receiver and it is also used to generate a template waveform for pulse reception. The latter requires the PLL to have quadrature outputs since the receiver uses I/Q reception. Because rather relaxed specifications in terms of phase-noise are required, a differential ring VCO with an even amount of stages is a suitable topology. The VCO has a measured center frequency of 568 MHz and a tuning range of 23%. It achieves a phase-noise of -91 dBc/Hz @ 1 MHz offset. The PLL employs a divide-by-8 and locks to an externally applied 75 MHz clock. Measurements show a total power consumption less than 200 muW with an rms jitter of 24 ps on an output clock of 600 MHz.