采用自抖动技术的11位1.2V 40.3μW SAR ADC

2016 IEEE MTT-S International Wireless Symposium (IWS) Pub Date : 2016-03-14 DOI:10.1109/IEEE-IWS.2016.7585432

Shuangshuang Zhang, Ting Li, Lele Jin, Jiaqi Yang, Lin He, F. Lin

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引用次数: 3

摘要

本文提出了一种采用自抖动技术的低功耗11位1毫秒/秒逐次逼近寄存器(SAR)模数转换器(ADC)。lbs被用作抖动来提高分辨率。仿真结果表明，与采用传统抖动结构的变换器相比，所提出的自抖动技术在简化硬件的基础上提高了DNL的性能。原型机采用180nm 1P6M CMOS和MOM电容制造。在1.2 v电源和1 MS/s下，布局后仿真结果显示，SNDR为63.8 dB，功耗为40.3μW，品质因数(FOM)为32 fJ/转换步长。芯片的总面积为1 mm×1 mm。

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A 11-bit 1.2V 40.3μW SAR ADC with self-dithering technique

This paper presents a low-power 11-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a self-dithering technique. The LSBs is employed as a dither to improve the resolution. Compared to converters that use the conventional dithering architecture, simulation results show that the proposed self-dithering technique improve the DNL performance with simplified hardware. The prototype is fabricated in 180nm 1P6M CMOS with MOM capacitor. At a 1.2-V supply and 1 MS/s, the post-layout simulation result shows an SNDR of 63.8 dB and consumes 40.3μW, and a figure of merit (FOM) of 32 fJ/conversion-step. The total area of the chip is 1 mm×1 mm.

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2016 IEEE MTT-S International Wireless Symposium (IWS)

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