压控晶体振荡器的幅值和工作点控制

T. Wey
{"title":"压控晶体振荡器的幅值和工作点控制","authors":"T. Wey","doi":"10.1109/MWSCAS.2007.4488575","DOIUrl":null,"url":null,"abstract":"In this work, a system architecture is presented for a voltage-controlled crystal oscillator (VCXO) with integrated Pierce structure and varactors in a deep submicron CMOS process. To meet low crystal drive, wide pull range, and negative resistance specifications in a low power supply leads to Pierce VCXO designs requiring both amplitude and operating point regulation. In this design, an automatic amplitude control (AAC) loop and embedded replica bias are implemented with the Pierce cell to provide the required regulation.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"On amplitude and operating point control of a voltage-controlled crystal oscillator\",\"authors\":\"T. Wey\",\"doi\":\"10.1109/MWSCAS.2007.4488575\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, a system architecture is presented for a voltage-controlled crystal oscillator (VCXO) with integrated Pierce structure and varactors in a deep submicron CMOS process. To meet low crystal drive, wide pull range, and negative resistance specifications in a low power supply leads to Pierce VCXO designs requiring both amplitude and operating point regulation. In this design, an automatic amplitude control (AAC) loop and embedded replica bias are implemented with the Pierce cell to provide the required regulation.\",\"PeriodicalId\":256061,\"journal\":{\"name\":\"2007 50th Midwest Symposium on Circuits and Systems\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 50th Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2007.4488575\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 50th Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2007.4488575","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

本文提出了一种在深亚微米CMOS工艺中集成Pierce结构和变容管的压控晶体振荡器(VCXO)的系统架构。为了满足低功耗下的低晶体驱动、宽拉力范围和负电阻规格,皮尔斯VCXO设计需要幅度和工作点调节。在这个设计中,一个自动幅度控制(AAC)回路和嵌入的复制偏差与皮尔斯单元实现,以提供所需的调节。
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On amplitude and operating point control of a voltage-controlled crystal oscillator
In this work, a system architecture is presented for a voltage-controlled crystal oscillator (VCXO) with integrated Pierce structure and varactors in a deep submicron CMOS process. To meet low crystal drive, wide pull range, and negative resistance specifications in a low power supply leads to Pierce VCXO designs requiring both amplitude and operating point regulation. In this design, an automatic amplitude control (AAC) loop and embedded replica bias are implemented with the Pierce cell to provide the required regulation.
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