Design-oriented delay model for CMOS inverter

This paper presents a new design oriented model for estimating the delay of a CMOS inverter. The model considers the impact of input transition time, input-to-output coupling capacitance, and physical effects such as drain-induced barrier lowering (DIBL) and velocity saturation. Thus, it is quite suitable for nanometer technologies. Moreover, no fitting parameters are required. Results are in very good agreement with HSPICE simulations based on BSIM4 transistor model over a wide range of input slopes and output loads, considering different inverter configurations. An average error of 3% in correlation to HSPICE has been attained.