Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344444
Matheus T. Moreira, R. Guazzelli, Ney Laert Vilar Calazans
The scaling of microelectronic technologies brings new challenges to the design of complex SoCs. For example, fully synchronous SoCs may soon become unfeasible to build. Asynchronous design techniques increasingly mingle within SoC design procedures to achieve functional and efficient systems, where synchronous modules are independently designed and verified. This is followed by module integration by means of asynchronous interfaces and communication architectures, forming a globally asynchronous, locally synchronous (GALS) system. Among multiple asynchronous design styles, the quasi delay insensitive (QDI) stands out for its robustness to delay variations. When coupled to delay insensitive (DI) codes like m-of-n and to four-phase handshake protocols, the QDI style produces the dominant asynchronous template currently in use. This work presents a technique to reduce the static power consumption of asynchronous QDI circuits using any m-of-n code and a four-phase handshake protocol, by proposing the utilization of a non-classical spacer encoding, namely all-1s. The article shows that the use of the traditional all-0s spacers may lead to static power consumption figures that are in some cases more than twice larger than the static power consumed by all-1s spacers in C-elements, the most common device used in asynchronous templates. Experiments demonstrate the new spacer reduces static power consumption without increase in complexity.
{"title":"Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes","authors":"Matheus T. Moreira, R. Guazzelli, Ney Laert Vilar Calazans","doi":"10.1109/SBCCI.2012.6344444","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344444","url":null,"abstract":"The scaling of microelectronic technologies brings new challenges to the design of complex SoCs. For example, fully synchronous SoCs may soon become unfeasible to build. Asynchronous design techniques increasingly mingle within SoC design procedures to achieve functional and efficient systems, where synchronous modules are independently designed and verified. This is followed by module integration by means of asynchronous interfaces and communication architectures, forming a globally asynchronous, locally synchronous (GALS) system. Among multiple asynchronous design styles, the quasi delay insensitive (QDI) stands out for its robustness to delay variations. When coupled to delay insensitive (DI) codes like m-of-n and to four-phase handshake protocols, the QDI style produces the dominant asynchronous template currently in use. This work presents a technique to reduce the static power consumption of asynchronous QDI circuits using any m-of-n code and a four-phase handshake protocol, by proposing the utilization of a non-classical spacer encoding, namely all-1s. The article shows that the use of the traditional all-0s spacers may lead to static power consumption figures that are in some cases more than twice larger than the static power consumed by all-1s spacers in C-elements, the most common device used in asynchronous templates. Experiments demonstrate the new spacer reduces static power consumption without increase in complexity.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116887783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344452
V. Possani, F. Marques, L. Rosa, V. Callegaro, A. Reis, R. Ribas
The transistor arrangement optimization is an effective possibility to improve logic gates and, consequently, VLSI design. This paper presents a graph-based methodology to determine if an ISOP may be implemented in non-series-parallel (NSP) switch arrangement. The proposed method aims to combine the cubes of such ISOP to build a graph where the vertices represent the cubes and the edges exist whether the vertices have common literals. Hence, if the obtained graph has the same topology of a `bridge' arrangement and each cube has all literals shared through the edges, this ISOP may be efficiently implemented through a NSP transistor network. The experiments were performed over the set of 4-input P-class Boolean functions, and the results were compared to the Moore's catalog. These experiments demonstrate that the proposed method tends to deliver optimal solutions for unate functions. Moreover, the method was able to determine equivalent SP or NSP transistor arrangements in 82.69% of the cases when considering a set of non-unate functions.
{"title":"NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements","authors":"V. Possani, F. Marques, L. Rosa, V. Callegaro, A. Reis, R. Ribas","doi":"10.1109/SBCCI.2012.6344452","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344452","url":null,"abstract":"The transistor arrangement optimization is an effective possibility to improve logic gates and, consequently, VLSI design. This paper presents a graph-based methodology to determine if an ISOP may be implemented in non-series-parallel (NSP) switch arrangement. The proposed method aims to combine the cubes of such ISOP to build a graph where the vertices represent the cubes and the edges exist whether the vertices have common literals. Hence, if the obtained graph has the same topology of a `bridge' arrangement and each cube has all literals shared through the edges, this ISOP may be efficiently implemented through a NSP transistor network. The experiments were performed over the set of 4-input P-class Boolean functions, and the results were compared to the Moore's catalog. These experiments demonstrate that the proposed method tends to deliver optimal solutions for unate functions. Moreover, the method was able to determine equivalent SP or NSP transistor arrangements in 82.69% of the cases when considering a set of non-unate functions.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130596627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344433
Abdulaziz Alhussien, N. Bagherzadeh, Freek Verbeek, B. V. Gastel, J. Schmaltz
A novel fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The routing function guarantees absence of deadlocks and livelocks up to two faulty channels. The routing logic does not require reconfiguration when a fault occurs. The routes themselves are dynamic. Based on the faults in the network, alternative routes are used to reroute packets. Routing decisions are based only on local knowledge, which allows for fast switching. Our approach does not use any costly virtual channels. As we do not prohibit cyclic dependencies, the routing function provides minimal routing from source to destination even in the presence of faults. We have implemented the architecture design using synthesizable HDL. To ensure deadlock freedom, we have extended a formally verified deadlock detection algorithm to deal with fault tolerant designs. For a 20×20 mesh, we have formally proven deadlock freedom of our design in all of the 2,878,800 configurations in which two channels are faulty. We supply experimental results showing the performance of our architecture.
{"title":"A formally verified deadlock-free routing function in a fault-tolerant NoC architecture","authors":"Abdulaziz Alhussien, N. Bagherzadeh, Freek Verbeek, B. V. Gastel, J. Schmaltz","doi":"10.1109/SBCCI.2012.6344433","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344433","url":null,"abstract":"A novel fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The routing function guarantees absence of deadlocks and livelocks up to two faulty channels. The routing logic does not require reconfiguration when a fault occurs. The routes themselves are dynamic. Based on the faults in the network, alternative routes are used to reroute packets. Routing decisions are based only on local knowledge, which allows for fast switching. Our approach does not use any costly virtual channels. As we do not prohibit cyclic dependencies, the routing function provides minimal routing from source to destination even in the presence of faults. We have implemented the architecture design using synthesizable HDL. To ensure deadlock freedom, we have extended a formally verified deadlock detection algorithm to deal with fault tolerant designs. For a 20×20 mesh, we have formally proven deadlock freedom of our design in all of the 2,878,800 configurations in which two channels are faulty. We supply experimental results showing the performance of our architecture.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126415985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344420
Y. N. Batista, C. Araujo, A. Silva-Filho
This work presents a FPGA design for real time flaw detection on edges based on LEDges technique. The LEDges, on one hand, significantly reduces the computational effort to perform the image segmentation, representation and description. On the other hand reduces the use of costly architectural resources such as processor and memory. Thus the FPGA design of the LEDges allows the implementation of automated visual inspection systems satisfying the increasing demand for performance. We have developed, implemented and applied the FPGA design to a real industrial problem, where defects were successfully detected on edges of toothpaste tubes. We achieve lower response time and lower use of computational resources than other solutions which have same computational complexity.
{"title":"FPGA design for real time flaw detection on edges using the LEDges technique","authors":"Y. N. Batista, C. Araujo, A. Silva-Filho","doi":"10.1109/SBCCI.2012.6344420","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344420","url":null,"abstract":"This work presents a FPGA design for real time flaw detection on edges based on LEDges technique. The LEDges, on one hand, significantly reduces the computational effort to perform the image segmentation, representation and description. On the other hand reduces the use of costly architectural resources such as processor and memory. Thus the FPGA design of the LEDges allows the implementation of automated visual inspection systems satisfying the increasing demand for performance. We have developed, implemented and applied the FPGA design to a real industrial problem, where defects were successfully detected on edges of toothpaste tubes. We achieve lower response time and lower use of computational resources than other solutions which have same computational complexity.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117090360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344423
Z. Bhatti, Narasinga Rao Miniskar, D. Preuveneers, Roel Wuyts, Y. Berbers, F. Catthoor
Scheduling and executing software efficiently on contemporary embedded systems, featuring heterogeneous multi-processors, multiple power modes, complex memory hierarchies and advanced interconnects, is a daunting task. State-of-the-art tools that schedule software tasks to hardware resources face limitations: (1) either they do not take into account the interdependancies among processing, memory and communication constraints (2) or they decouple the problem of spatial assignment from temporal scheduling. As a result existing tools make sub-optimal spatio-temporal scheduling decisions. This paper presents a technique to find globally optimized solutions by co-exploring spatio-temporal schedules for computation, data storage and communication simultaneously, considering the interdependencies between them. Experiments on mapping exploration of an image processing application on a heterogeneous MPSoC platform show that this co-exploration methodology finds schedules that are more energy efficient, when compared to decoupled exploration techniques for the particular application and target platform.
{"title":"Memory and communication driven spatio-temporal scheduling on MPSoCs","authors":"Z. Bhatti, Narasinga Rao Miniskar, D. Preuveneers, Roel Wuyts, Y. Berbers, F. Catthoor","doi":"10.1109/SBCCI.2012.6344423","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344423","url":null,"abstract":"Scheduling and executing software efficiently on contemporary embedded systems, featuring heterogeneous multi-processors, multiple power modes, complex memory hierarchies and advanced interconnects, is a daunting task. State-of-the-art tools that schedule software tasks to hardware resources face limitations: (1) either they do not take into account the interdependancies among processing, memory and communication constraints (2) or they decouple the problem of spatial assignment from temporal scheduling. As a result existing tools make sub-optimal spatio-temporal scheduling decisions. This paper presents a technique to find globally optimized solutions by co-exploring spatio-temporal schedules for computation, data storage and communication simultaneously, considering the interdependencies between them. Experiments on mapping exploration of an image processing application on a heterogeneous MPSoC platform show that this co-exploration methodology finds schedules that are more energy efficient, when compared to decoupled exploration techniques for the particular application and target platform.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121680459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344439
Y. Ghidini, T. Webber, E. I. Moreno, Ivan Quadros, R. Fagundes, C. Marcon
NoC has emerged as as efficient communication infrastructure to fulfill the heavy communication requirements of several applications, which are implemented on MPSoC target architectures. 2D NoCs are natural choices of communication infrastructure for the majority of actual chip fabrication technologies. However, wire delay and power consumption are dramatically increasing even when using this kind of topology. In this sense, 3D NoC emerges as an improvement of 2D NoC aiming to reduce the length and number of global interconnections. This work explores architectural impacts of 2D and 3D NoC topologies on latency, throughput and network occupancy. We show that, in average, 3D topologies minimize 30% the application latency and increase 56% the packets throughput, when compared to 2D topologies. In addition, the paper explores the influence of the buffer length on communication architecture latency and on application latency, highlighting that when applying an appropriate buffer length the application latency in reduced up to 3.4 times for 2D topologies and 2.3 times for 3D topologies.
{"title":"Topological impact on latency and throughput: 2D versus 3D NoC comparison","authors":"Y. Ghidini, T. Webber, E. I. Moreno, Ivan Quadros, R. Fagundes, C. Marcon","doi":"10.1109/SBCCI.2012.6344439","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344439","url":null,"abstract":"NoC has emerged as as efficient communication infrastructure to fulfill the heavy communication requirements of several applications, which are implemented on MPSoC target architectures. 2D NoCs are natural choices of communication infrastructure for the majority of actual chip fabrication technologies. However, wire delay and power consumption are dramatically increasing even when using this kind of topology. In this sense, 3D NoC emerges as an improvement of 2D NoC aiming to reduce the length and number of global interconnections. This work explores architectural impacts of 2D and 3D NoC topologies on latency, throughput and network occupancy. We show that, in average, 3D topologies minimize 30% the application latency and increase 56% the packets throughput, when compared to 2D topologies. In addition, the paper explores the influence of the buffer length on communication architecture latency and on application latency, highlighting that when applying an appropriate buffer length the application latency in reduced up to 3.4 times for 2D topologies and 2.3 times for 3D topologies.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131531315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344425
C. Cruz, Israel L. Marinho, D. Monteiro
The pseudo-flash reset (P-FRST) is a technique used to reduce image lag in CMOS active-pixel sensors (APS). The compact pixel topology consisting of a photodetector and three FETs (3T APS) is widely employed because of its large fill factor combined with the possibility to operate in both linear and logarithmic compressed-response (LCR) modes. The use of these two modes in a single readout cycle yields good low-light sensitivity and extended dynamic range (DR). However, fabrication non idealities result in fixed-pattern noise (FPN) across the image-sensor chip and cannot be reduced by classical double-sampling readout subtraction (DSRS). In the present work, we propose an extended use of the P-FRST technique to provide an adequate voltage reference on pixel, in order to enable DSRS, thus reducing FPN in conventional 3T APS operating in mixed linear-LCR mode.
{"title":"Extended use of pseudo-flash reset technique for an active pixel with logarithmic compressed response","authors":"C. Cruz, Israel L. Marinho, D. Monteiro","doi":"10.1109/SBCCI.2012.6344425","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344425","url":null,"abstract":"The pseudo-flash reset (P-FRST) is a technique used to reduce image lag in CMOS active-pixel sensors (APS). The compact pixel topology consisting of a photodetector and three FETs (3T APS) is widely employed because of its large fill factor combined with the possibility to operate in both linear and logarithmic compressed-response (LCR) modes. The use of these two modes in a single readout cycle yields good low-light sensitivity and extended dynamic range (DR). However, fabrication non idealities result in fixed-pattern noise (FPN) across the image-sensor chip and cannot be reduced by classical double-sampling readout subtraction (DSRS). In the present work, we propose an extended use of the P-FRST technique to provide an adequate voltage reference on pixel, in order to enable DSRS, thus reducing FPN in conventional 3T APS operating in mixed linear-LCR mode.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132761564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344447
R. C. Sampaio, P. Berger, R. Jacobi
This paper presents a HW/SW Co-design of an AAC-LC audio decoder implemented on an FPGA. The complexity of each decoding step is analyzed and the decoding modules are classified by their computational requirements. The result is a balanced design with software modules running on a processor used to implement the various types of AAC input formats (MP4 Standard files and LATM/LOAS Stream) as well as the bitstream parser. Hardware modules are used for the calculation intensive parts of the algorithm (Huffman Decoding, Spectral Tools, Filterbank). The integrated design is implemented on an Altera Cyclone II FPGA with NIOS II/s as a processor and was able to decode 5.1 (6 channels) audio wavefiles running at 50MHz while other FPGA designs seen on literature decode only 2 channels with half the frequency.
本文提出了一种基于FPGA的AAC-LC音频解码器软硬件协同设计方案。分析了每个解码步骤的复杂度，并根据解码模块的计算需求对其进行了分类。结果是一个平衡的设计，软件模块运行在一个处理器上，用于实现各种类型的AAC输入格式(MP4标准文件和LATM/LOAS流)以及位流解析器。硬件模块用于算法的计算密集部分(霍夫曼解码，频谱工具，滤波器组)。集成设计在Altera Cyclone II FPGA上实现，NIOS II/s作为处理器，能够解码运行在50MHz的5.1(6通道)音频波文件，而文献中看到的其他FPGA设计仅解码2通道，频率为一半。
{"title":"Hardware and software co-design for the AAC audio decoder","authors":"R. C. Sampaio, P. Berger, R. Jacobi","doi":"10.1109/SBCCI.2012.6344447","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344447","url":null,"abstract":"This paper presents a HW/SW Co-design of an AAC-LC audio decoder implemented on an FPGA. The complexity of each decoding step is analyzed and the decoding modules are classified by their computational requirements. The result is a balanced design with software modules running on a processor used to implement the various types of AAC input formats (MP4 Standard files and LATM/LOAS Stream) as well as the bitstream parser. Hardware modules are used for the calculation intensive parts of the algorithm (Huffman Decoding, Spectral Tools, Filterbank). The integrated design is implemented on an Altera Cyclone II FPGA with NIOS II/s as a processor and was able to decode 5.1 (6 channels) audio wavefiles running at 50MHz while other FPGA designs seen on literature decode only 2 channels with half the frequency.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129322420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344441
Ricardo Vanni Dallasen, G. Wirth, T. H. Both
This paper presents a PLL scheme for clock generation with a Total Ionizing Dose (TID) degradation detector. Externally to the PLL circuitry, when the degradation due to TID effects reaches a certain predefined threshold, the circuit reduces the clock frequency output. To compensate for the increased delay caused by the total dose effect (TID), the system increases the clock period in order to avoid timing violations, increasing the chip lifespan. The circuit was designed in a 0.35μm CMOS process and simulated with HSPICE tool.
{"title":"A PLL for clock generation with automatic frequency control under TID effects","authors":"Ricardo Vanni Dallasen, G. Wirth, T. H. Both","doi":"10.1109/SBCCI.2012.6344441","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344441","url":null,"abstract":"This paper presents a PLL scheme for clock generation with a Total Ionizing Dose (TID) degradation detector. Externally to the PLL circuitry, when the degradation due to TID effects reaches a certain predefined threshold, the circuit reduces the clock frequency output. To compensate for the increased delay caused by the total dose effect (TID), the system increases the clock period in order to avoid timing violations, increasing the chip lifespan. The circuit was designed in a 0.35μm CMOS process and simulated with HSPICE tool.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128923335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344421
Bo Huang, Song Chen, Wei Zhong, T. Yoshimura
Application-Specific Network-on-Chip (ASNoC) architecture is more promising than regular network-on-Chip(NoC) for some particular applications. In ASNoC Design, one of the key challenges is to generate the most suitable and power efficient NoC topology. In previous works, the placement of the cores and network components, and the path allocation are explored separately. However, the path allocation strongly depends on the placement of cores and network components. In this paper, we integrate these steps together through the floorplanning with the cluster reconstruction and path allocation (FCRPA). Several SoC benchmarks have been tested and the results showed improvements over the latest works.
{"title":"Application-Specific Network-on-Chip synthesis with topology-aware floorplanning","authors":"Bo Huang, Song Chen, Wei Zhong, T. Yoshimura","doi":"10.1109/SBCCI.2012.6344421","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344421","url":null,"abstract":"Application-Specific Network-on-Chip (ASNoC) architecture is more promising than regular network-on-Chip(NoC) for some particular applications. In ASNoC Design, one of the key challenges is to generate the most suitable and power efficient NoC topology. In previous works, the placement of the cores and network components, and the path allocation are explored separately. However, the path allocation strongly depends on the placement of cores and network components. In this paper, we integrate these steps together through the floorplanning with the cluster reconstruction and path allocation (FCRPA). Several SoC benchmarks have been tested and the results showed improvements over the latest works.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121668669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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