基于65nm CMOS的8位450毫秒/秒单位/周期SAR ADC

2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI:10.1109/ESSCIRC.2013.6649086

Vaibhav Tripathi, B. Murmann

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引用次数: 53

摘要

提出了一种低功耗的8位450毫秒/秒单比特/周期SAR ADC。该设计结合了顶板采样、小单位电容(0.75 fF)、对称DAC开关和围绕单个高速比较器的明智延迟优化，在奈奎斯特实现了7.6的ENOB，转化为76 fJ/转换步长的FOM。该转换器在65纳米CMOS中占据0.035 mm2的有源面积。

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An 8-bit 450-MS/s single-bit/cycle SAR ADC in 65-nm CMOS

A low-energy 8-bit 450-MS/s single-bit/cycle SAR ADC is presented. The design combines top-plate sampling, small unit capacitances (0.75 fF), symmetric DAC switching, and judicious delay optimization around a single high-speed comparator to achieve an ENOB of 7.6 at Nyquist, translating into an FOM of 76 fJ/conversion-step. The converter occupies an active area of 0.035 mm2 in 65-nm CMOS.

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2013 Proceedings of the ESSCIRC (ESSCIRC)

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