A double trench 4H — SiC MOSFET as an enhanced model of SiC UMOSFET

In this paper, a double trench 4H SiC MOSFET is presented as an enhanced model for the SiC conventional UMOSFET with a p+ shielding to prevent dielectric breakdown of the gate oxide. This paper proposes a double trench structure with both gate and source trenches. The double trench structure reduces the electric field at the bottom of the gate oxide. Thus, on optimizing the model of UMOSFET with Double Trench structure we further increase the breakdown voltage (BV). Hence, higher BV is achieved compared to conventional SiC UMOSFET, resulting in increase of overall figure of merit (FoM) to an appreciable value. The BV achieved is 1450 V and ON-state specific resistance (RON-sp) is 4.24 mΩ.cm2 which on calculation gives FoM to be 0.495. Thus, the FoM is improved by 36.3% compared to conventional SiC UMOSFET.