130nm功率SOI工艺中高压NPN ESD保护器件的设计优化

2020 International EOS/ESD Symposium on Design and System (IEDS) Pub Date : 2021-06-23 DOI:10.23919/IEDS48938.2021.9468844

Raunak Kumar, J. Zeng, K. Hwang, R. Gauthier

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引用次数: 0

摘要

采用130nm Power SOI技术对HV NPN ESD器件进行了评估。利用TCAD研究了静电放电应力下的电流和温度分布，并提出了一种新的器件结构。研究了非均匀触发问题。分段式布局设计，多指设备触发均匀。

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Design Optimization of High Voltage NPN ESD Protection Device in 130nm Power SOI Technology

A HV NPN ESD devices is evaluated in a 130nm Power SOI technology. Current flow and temperature distribution under ESD stress is investigated by TCAD and a new device architecture without STI is proposed. Non-uniform triggering issue is also investigated. Segment type layout design shows uniform triggering of multi-finger devices.

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2020 International EOS/ESD Symposium on Design and System (IEDS)

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