Pub Date : 2021-06-23DOI: 10.23919/IEDS48938.2021.9468844
Raunak Kumar, J. Zeng, K. Hwang, R. Gauthier
A HV NPN ESD devices is evaluated in a 130nm Power SOI technology. Current flow and temperature distribution under ESD stress is investigated by TCAD and a new device architecture without STI is proposed. Non-uniform triggering issue is also investigated. Segment type layout design shows uniform triggering of multi-finger devices.
采用130nm Power SOI技术对HV NPN ESD器件进行了评估。利用TCAD研究了静电放电应力下的电流和温度分布，并提出了一种新的器件结构。研究了非均匀触发问题。分段式布局设计，多指设备触发均匀。
{"title":"Design Optimization of High Voltage NPN ESD Protection Device in 130nm Power SOI Technology","authors":"Raunak Kumar, J. Zeng, K. Hwang, R. Gauthier","doi":"10.23919/IEDS48938.2021.9468844","DOIUrl":"https://doi.org/10.23919/IEDS48938.2021.9468844","url":null,"abstract":"A HV NPN ESD devices is evaluated in a 130nm Power SOI technology. Current flow and temperature distribution under ESD stress is investigated by TCAD and a new device architecture without STI is proposed. Non-uniform triggering issue is also investigated. Segment type layout design shows uniform triggering of multi-finger devices.","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127350867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-23DOI: 10.23919/IEDS48938.2021.9468869
Xiaotian Chen, Yize Wang, Yuan Wang
To study the electrostatic discharge (ESD) characteristics of the full-depleted silicon-on-isolation (FD-SOI) device, some ESD structures are fabricated in a 22-nm FD-SOI process. The DC and TLP experimental testing have been fulfilled and investigated.
{"title":"Experimental investigation of ESD protection for a 22-nm FD-SOI process","authors":"Xiaotian Chen, Yize Wang, Yuan Wang","doi":"10.23919/IEDS48938.2021.9468869","DOIUrl":"https://doi.org/10.23919/IEDS48938.2021.9468869","url":null,"abstract":"To study the electrostatic discharge (ESD) characteristics of the full-depleted silicon-on-isolation (FD-SOI) device, some ESD structures are fabricated in a 22-nm FD-SOI process. The DC and TLP experimental testing have been fulfilled and investigated.","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128287352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-23DOI: 10.23919/IEDS48938.2021.9468856
Xiaoyun Li, Lihui Wang, Guangyi Lu, Xin Gao, Mei Li
A novel area-efficient ESD power clamp with enhanced noise immunity is proposed. This design can extend on-time of big MOSFET and reuse shutoff NMOS transistor to reduce detection circuit's area. The 29% reduction of detection circuit's area is achieved. The verification is done under an advanced FinFET process.
{"title":"A Novel Area-Efficient ESD Power Clamp with Enhanced Noise Immunity","authors":"Xiaoyun Li, Lihui Wang, Guangyi Lu, Xin Gao, Mei Li","doi":"10.23919/IEDS48938.2021.9468856","DOIUrl":"https://doi.org/10.23919/IEDS48938.2021.9468856","url":null,"abstract":"A novel area-efficient ESD power clamp with enhanced noise immunity is proposed. This design can extend on-time of big MOSFET and reuse shutoff NMOS transistor to reduce detection circuit's area. The 29% reduction of detection circuit's area is achieved. The verification is done under an advanced FinFET process.","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130936202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-23DOI: 10.23919/IEDS48938.2021.9468827
Prantik Mahajan, Raunak Kumar, R. Gauthier, K. Hwang
Design optimization of Electrostatic Discharge (ESD) GGNMOS for high-voltage applications in low-cost BCDLite technology is reported. Clamp performance optimization through body PWELL engineering and device design techniques are investigated. A comparative analysis between two distinct device architectures (different Poly-LOCOS overlap) showing 100ns TLP measurement and TCAD simulation results is presented.
{"title":"Optimization of GGNMOS Devices for High-Voltage ESD Protection in BCDLite Technology","authors":"Prantik Mahajan, Raunak Kumar, R. Gauthier, K. Hwang","doi":"10.23919/IEDS48938.2021.9468827","DOIUrl":"https://doi.org/10.23919/IEDS48938.2021.9468827","url":null,"abstract":"Design optimization of Electrostatic Discharge (ESD) GGNMOS for high-voltage applications in low-cost BCDLite technology is reported. Clamp performance optimization through body PWELL engineering and device design techniques are investigated. A comparative analysis between two distinct device architectures (different Poly-LOCOS overlap) showing 100ns TLP measurement and TCAD simulation results is presented.","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124105587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-23DOI: 10.23919/IEDS48938.2021.9468824
M. Miao, You Li, Wei Liang, R. Gauthier
Diode trigger SCR (DTSCR) structure is introduced in FinFET technology for low voltage circuit ESD protection. The current direction is chosen to flow vertically down through the fins to make full use of the bulk silicon region. Further optimization of DTSCR is investigated to improve layout efficiency.
{"title":"Design and Optimization of Diode Triggered Silicon Controlled Rectifier in FinFET Technology","authors":"M. Miao, You Li, Wei Liang, R. Gauthier","doi":"10.23919/IEDS48938.2021.9468824","DOIUrl":"https://doi.org/10.23919/IEDS48938.2021.9468824","url":null,"abstract":"Diode trigger SCR (DTSCR) structure is introduced in FinFET technology for low voltage circuit ESD protection. The current direction is chosen to flow vertically down through the fins to make full use of the bulk silicon region. Further optimization of DTSCR is investigated to improve layout efficiency.","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128836603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-23DOI: 10.23919/IEDS48938.2021.9468852
Xiangliang Jin, Yang Wang
Dual Direction Silicon Controlled Rectifier(DDSCR) are primarily used for ESD protection in high voltage environments. According to the results of the device test, the trigger voltage and the sustain voltage of the DDSCR are 17.62V and 9.54V, respectively. Finally, by changing the important dimensions of the DDSCR, the ESD characteristics of the device can be significantly improved.
{"title":"DDSCR Device Structure Fabricated on 0.5 µm CMOS Process","authors":"Xiangliang Jin, Yang Wang","doi":"10.23919/IEDS48938.2021.9468852","DOIUrl":"https://doi.org/10.23919/IEDS48938.2021.9468852","url":null,"abstract":"Dual Direction Silicon Controlled Rectifier(DDSCR) are primarily used for ESD protection in high voltage environments. According to the results of the device test, the trigger voltage and the sustain voltage of the DDSCR are 17.62V and 9.54V, respectively. Finally, by changing the important dimensions of the DDSCR, the ESD characteristics of the device can be significantly improved.","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122427438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-23DOI: 10.23919/IEDS48938.2021.9468862
Zeyu Zhong, Xiangliang Jin
Based on a LDMOS-SCR designed and manufactured in 0.5µm CMOS process, a SCR equivalent circuit model for ESD protection is applied and verified. Simulation results show a high consistency with the TLP 1-V curve. It contributes to the simulation methodology of SCR devices for ESD protection.
{"title":"Verification of an Equivalent Circuit Model for LDMOS-SCR Based on 0.5 µm CMOS Process","authors":"Zeyu Zhong, Xiangliang Jin","doi":"10.23919/IEDS48938.2021.9468862","DOIUrl":"https://doi.org/10.23919/IEDS48938.2021.9468862","url":null,"abstract":"Based on a LDMOS-SCR designed and manufactured in 0.5µm CMOS process, a SCR equivalent circuit model for ESD protection is applied and verified. Simulation results show a high consistency with the TLP 1-V curve. It contributes to the simulation methodology of SCR devices for ESD protection.","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122444701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-23DOI: 10.23919/IEDS48938.2021.9468822
J. Zeng, Raunak Kumar, T. Tsai, Sevashanmugam Marimuthu, R. Gauthier
This paper presents a high voltage NPN based ESD protection device with a designed PBL under collector region. Experiment on silicon shows it achieves 2.7X failure current improvement compared to structure without PBL. It has a flexible feature of tunable trigger voltage and holding voltage without It2 degradation.
{"title":"Optimization of NPN ESD Protection Device for Improved Failure Current","authors":"J. Zeng, Raunak Kumar, T. Tsai, Sevashanmugam Marimuthu, R. Gauthier","doi":"10.23919/IEDS48938.2021.9468822","DOIUrl":"https://doi.org/10.23919/IEDS48938.2021.9468822","url":null,"abstract":"This paper presents a high voltage NPN based ESD protection device with a designed PBL under collector region. Experiment on silicon shows it achieves 2.7X failure current improvement compared to structure without PBL. It has a flexible feature of tunable trigger voltage and holding voltage without It2 degradation.","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116161323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-23DOI: 10.23919/ieds48938.2021.9468857
{"title":"General Chair Letter","authors":"","doi":"10.23919/ieds48938.2021.9468857","DOIUrl":"https://doi.org/10.23919/ieds48938.2021.9468857","url":null,"abstract":"","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126313064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-23DOI: 10.23919/IEDS48938.2021.9468834
Yunhao Li, Yize Wang, Yuan Wang
As CMOS scales down to FinFET technology, the performance of ESD devices degenerates seriously. In this work, two types of ESD protection diodes, Gated Diode and STI Diode, are investigatedin 14nm FinFET technology. The corresponding 3D TCAD simulation helps to understand the working mechanism for the above two diodes.
{"title":"ESD Diode Devices Simulation and Analysis in a FinFET Technology","authors":"Yunhao Li, Yize Wang, Yuan Wang","doi":"10.23919/IEDS48938.2021.9468834","DOIUrl":"https://doi.org/10.23919/IEDS48938.2021.9468834","url":null,"abstract":"As CMOS scales down to FinFET technology, the performance of ESD devices degenerates seriously. In this work, two types of ESD protection diodes, Gated Diode and STI Diode, are investigatedin 14nm FinFET technology. The corresponding 3D TCAD simulation helps to understand the working mechanism for the above two diodes.","PeriodicalId":174954,"journal":{"name":"2020 International EOS/ESD Symposium on Design and System (IEDS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127478353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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