D. Crestani, A. Aguila, M. Gentil, P. Chardon, C. Durante
{"title":"用于确定性测试的自动分区","authors":"D. Crestani, A. Aguila, M. Gentil, P. Chardon, C. Durante","doi":"10.1109/EURDAC.1992.246224","DOIUrl":null,"url":null,"abstract":"Automatic partitioning for digital circuits is proposed. The partitions are defined by using functional testability measures and a test difficulty estimation. The software, developed with an expert system generator, is embedded in a hierarchical test generation process. The partitioning technique proposed uses difficulty test estimation corresponding to the maximal number of logical gates that can be embedded in a given partition. This parameter represents the maximal number of gates that can be handled by the tool.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Automatic partitioning for deterministic test\",\"authors\":\"D. Crestani, A. Aguila, M. Gentil, P. Chardon, C. Durante\",\"doi\":\"10.1109/EURDAC.1992.246224\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Automatic partitioning for digital circuits is proposed. The partitions are defined by using functional testability measures and a test difficulty estimation. The software, developed with an expert system generator, is embedded in a hierarchical test generation process. The partitioning technique proposed uses difficulty test estimation corresponding to the maximal number of logical gates that can be embedded in a given partition. This parameter represents the maximal number of gates that can be handled by the tool.<<ETX>>\",\"PeriodicalId\":218056,\"journal\":{\"name\":\"Proceedings EURO-DAC '92: European Design Automation Conference\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings EURO-DAC '92: European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1992.246224\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings EURO-DAC '92: European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1992.246224","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Automatic partitioning for digital circuits is proposed. The partitions are defined by using functional testability measures and a test difficulty estimation. The software, developed with an expert system generator, is embedded in a hierarchical test generation process. The partitioning technique proposed uses difficulty test estimation corresponding to the maximal number of logical gates that can be embedded in a given partition. This parameter represents the maximal number of gates that can be handled by the tool.<>
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