M. Lau, S. Shieh, Pei-Feng Wang, B. Smith, Min-Shueh Yuan, D. Lee, J. Gaba, J. Chao, B. Shung, C. Shih
{"title":"一个包内存集成的44gb /s交换处理器,带有10gb端口和12gb端口","authors":"M. Lau, S. Shieh, Pei-Feng Wang, B. Smith, Min-Shueh Yuan, D. Lee, J. Gaba, J. Chao, B. Shung, C. Shih","doi":"10.1109/ISSCC.2002.992096","DOIUrl":null,"url":null,"abstract":"A 44 Gb/s switching processor chip has 1 MB embedded packet memory. With a 10 Gb and 12 1 Gb ports, this chip is useful for LAN/WAN bridging applications. Wire-speed switching performance is demonstrated using a shared buffer switching architecture. This 0.18 μm CMOS processor integrates a 10 Gb port with an XGMII interface.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A packet-memory-integrated 44 Gb/s switching processor with a 10 Gb port and 12 Gb ports\",\"authors\":\"M. Lau, S. Shieh, Pei-Feng Wang, B. Smith, Min-Shueh Yuan, D. Lee, J. Gaba, J. Chao, B. Shung, C. Shih\",\"doi\":\"10.1109/ISSCC.2002.992096\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 44 Gb/s switching processor chip has 1 MB embedded packet memory. With a 10 Gb and 12 1 Gb ports, this chip is useful for LAN/WAN bridging applications. Wire-speed switching performance is demonstrated using a shared buffer switching architecture. This 0.18 μm CMOS processor integrates a 10 Gb port with an XGMII interface.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.992096\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992096","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A packet-memory-integrated 44 Gb/s switching processor with a 10 Gb port and 12 Gb ports
A 44 Gb/s switching processor chip has 1 MB embedded packet memory. With a 10 Gb and 12 1 Gb ports, this chip is useful for LAN/WAN bridging applications. Wire-speed switching performance is demonstrated using a shared buffer switching architecture. This 0.18 μm CMOS processor integrates a 10 Gb port with an XGMII interface.