Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, R. Krishnamurthy
{"title":"一个8核RISC-V处理器，在Intel 4 CMOS中具有接近最后一级缓存的计算","authors":"Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, R. Krishnamurthy","doi":"10.1109/vlsitechnologyandcir46769.2022.9830518","DOIUrl":null,"url":null,"abstract":"An 8-core 64b processor extends RISC-V to perform multiply accumulate within shared last level cache. Compute Near Last Level Cache (CNC) enables high-bandwidth access and local compute with the highest-capacity on-chip SRAM. The 1.15GHz chip expands virtual addressing, coherency, and consistency to CNC, enabling Linux-capable multi-core operation. CNC reduces energy by 52× for fully connected and 29× for convolutional DNN layers. MLPerf™ Anomaly Detection latency is reduced by 4.25× to 40μs.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS\",\"authors\":\"Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, R. Krishnamurthy\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830518\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 8-core 64b processor extends RISC-V to perform multiply accumulate within shared last level cache. Compute Near Last Level Cache (CNC) enables high-bandwidth access and local compute with the highest-capacity on-chip SRAM. The 1.15GHz chip expands virtual addressing, coherency, and consistency to CNC, enabling Linux-capable multi-core operation. CNC reduces energy by 52× for fully connected and 29× for convolutional DNN layers. MLPerf™ Anomaly Detection latency is reduced by 4.25× to 40μs.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830518\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830518","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS
An 8-core 64b processor extends RISC-V to perform multiply accumulate within shared last level cache. Compute Near Last Level Cache (CNC) enables high-bandwidth access and local compute with the highest-capacity on-chip SRAM. The 1.15GHz chip expands virtual addressing, coherency, and consistency to CNC, enabling Linux-capable multi-core operation. CNC reduces energy by 52× for fully connected and 29× for convolutional DNN layers. MLPerf™ Anomaly Detection latency is reduced by 4.25× to 40μs.
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