Optimization of Behavioral Modeling for Codesign of Embedded System

Behavioral modeling for codesign system is transformed into internal model known as control/data flow graph and produces a register-transfer-level (RTL) model of the hardware implementation for a given schedule. The internal model for codesign system is partitioned after scheduling and its communication cost is evaluated. The communication between components is through the buffered channels, the size of the buffer is estimated by its edge cut-set and system delay for different models are achieved to measure the quality of partitioning as opposed to general partitioning approaches that use number of nodes in each partition as constraint. In this paper scheduling and allocation algorithm (SAA) discusses helpful optimization method for resource-constrained and time constrained system in high level synthesis tool. The approach is based on data path for CDFG model that capture the design information from the source file specified by VHDL language from its equivalent separate Control flow graph and data flow graph. The proposed algorithm is also compared with other algorithm through estimation of schedules with a benchmark example. The buffer size is calculated with different objectives in partitioning and optimum partitioning is proposed