Component selection, scheduling and control schemes for high level synthesis

This paper emphasizes on the performance optimization problem of automatically synthesized circuits while respecting area constraints. This optimization is performed at the earliest step of synthesis, i.e. during the scheduling of the behavioral specification of the circuit. It is mainly based on an adequate determination of the type of component which implements each operation in the specification. An algorithm performing concurrently component selection and scheduling is presented. It gives the designer facilities for design-space exploration, i.e. time versus area, since components are taken from a user specified library. The special features of this algorithm are: several component types can implement an operation and one component type can implement several operations; the delays are associated to pairs (component type, operation type); both the usual synchronous control scheme and a control scheme allowing to tune independently the delay of every control step (referred as adjusted control) are discussed.<>