{"title":"第一款基于英特尔低成本IA原子的片上系统,用于上网本/上网本","authors":"S. Sutanthavibul, Suresh Kumar Perabala","doi":"10.1109/ASQED.2009.5206293","DOIUrl":null,"url":null,"abstract":"The paper describes a design IP-reuse methodology used in a new Intel Low Cost IA (LCIA) System-on-Chip (SoC) design, call Pineview (PNV). The PNV SoC is used in the next generation Intel Nettop/Netbook platform. The SoC chip integrates several Intel internal Intellectual Property (IP) blocks on the same die: mainly two Atom CPU cores, a Graphic engine, a memory controller, and IO interfaces. The IP-reuse methodology provides high design efficiency and productivity. It also allows flexibility and customization for lower power consumption and a floorplan optimization needed for the Nettop/Netbook market segment. The paper also provides an overview of the PNV based Nettop/Netbook platform architecture. It also explains IP-reuse methodology and full chip integration which is performed by a design team in Intel Penang Design Center.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"First Intel Low-Cost IA Atom-based System-On-Chip for Nettop/Netbook\",\"authors\":\"S. Sutanthavibul, Suresh Kumar Perabala\",\"doi\":\"10.1109/ASQED.2009.5206293\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper describes a design IP-reuse methodology used in a new Intel Low Cost IA (LCIA) System-on-Chip (SoC) design, call Pineview (PNV). The PNV SoC is used in the next generation Intel Nettop/Netbook platform. The SoC chip integrates several Intel internal Intellectual Property (IP) blocks on the same die: mainly two Atom CPU cores, a Graphic engine, a memory controller, and IO interfaces. The IP-reuse methodology provides high design efficiency and productivity. It also allows flexibility and customization for lower power consumption and a floorplan optimization needed for the Nettop/Netbook market segment. The paper also provides an overview of the PNV based Nettop/Netbook platform architecture. It also explains IP-reuse methodology and full chip integration which is performed by a design team in Intel Penang Design Center.\",\"PeriodicalId\":437303,\"journal\":{\"name\":\"2009 1st Asia Symposium on Quality Electronic Design\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 1st Asia Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASQED.2009.5206293\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 1st Asia Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASQED.2009.5206293","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
First Intel Low-Cost IA Atom-based System-On-Chip for Nettop/Netbook
The paper describes a design IP-reuse methodology used in a new Intel Low Cost IA (LCIA) System-on-Chip (SoC) design, call Pineview (PNV). The PNV SoC is used in the next generation Intel Nettop/Netbook platform. The SoC chip integrates several Intel internal Intellectual Property (IP) blocks on the same die: mainly two Atom CPU cores, a Graphic engine, a memory controller, and IO interfaces. The IP-reuse methodology provides high design efficiency and productivity. It also allows flexibility and customization for lower power consumption and a floorplan optimization needed for the Nettop/Netbook market segment. The paper also provides an overview of the PNV based Nettop/Netbook platform architecture. It also explains IP-reuse methodology and full chip integration which is performed by a design team in Intel Penang Design Center.