Electro-Thermomigration in NMOS LSI Devices

Electro-thermomigration (ETM) of aluminum metallization through contact windows into the substrate accounts for many of the burh-in failures for certain NMOS LSI devices. The developmental history of this failure mode was studied by an analysis of the failed devices and by controlled ESD stressing. The failure mode tends to preferentially occur at parasitic bipolar transistor sites which exhibit minimum BVCEO and which contain an aluminum contact window located close to the collector-base junction. By applying the mathematical model of Raburn and Causey1, the BVCEO values for two important parasitics are calculated as a function of layout and processing parameters. In combination with the ETM studies of Christou2, these results are used to generate layout recommendations which yield an improved resistance to the ETM failure mode.