Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.362987
J. Uebbing
One of the key reliability limitations of low cost encapsulated optoelectronic devices has been temperature cycling. This is because the clear polymers used to encapsulate the devices have expansion coefficients significantly greater than the devices to be encapsulated. This mismatch causes thermal stresses and cyclical stress causes low cycle fatigue failure.1 In this paper we show how the use of log-normal plots of the failure rate allows ready comparison of different device types and structures, extrapolation to different stress conditions and the examination of the statistical significance of the results. Two types of stress condition are distinguished, polymer motion and polymer force. In the polymer motion mode, the polymer portion is large and stiff compared to the rest of the device. In the polymer force mode, the polymer is small and/or soft compared to the device. In terms of device design, the two things that affect the mode and the temperature cycle reliability are structure and materials. In the structures area, a series of comparisons between elastic stress theory and observed failure rates is done for different device geometries. Stress concentrations around ceramic substrates, bending forces on ceramic substrates, stress concentrations around stiff lead frames, stress in wire loops and kink formation in gold wire are all examined. An integrated model for certain failure modes is proposed. In the materials area, the benefits of soft silicones and so-called magic epoxes are presented.
{"title":"Mechanisms of Temperature Cycle Failure in Encapsulated Optoelectronic Devices","authors":"J. Uebbing","doi":"10.1109/IRPS.1981.362987","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362987","url":null,"abstract":"One of the key reliability limitations of low cost encapsulated optoelectronic devices has been temperature cycling. This is because the clear polymers used to encapsulate the devices have expansion coefficients significantly greater than the devices to be encapsulated. This mismatch causes thermal stresses and cyclical stress causes low cycle fatigue failure.1 In this paper we show how the use of log-normal plots of the failure rate allows ready comparison of different device types and structures, extrapolation to different stress conditions and the examination of the statistical significance of the results. Two types of stress condition are distinguished, polymer motion and polymer force. In the polymer motion mode, the polymer portion is large and stiff compared to the rest of the device. In the polymer force mode, the polymer is small and/or soft compared to the device. In terms of device design, the two things that affect the mode and the temperature cycle reliability are structure and materials. In the structures area, a series of comparisons between elastic stress theory and observed failure rates is done for different device geometries. Stress concentrations around ceramic substrates, bending forces on ceramic substrates, stress concentrations around stiff lead frames, stress in wire loops and kink formation in gold wire are all examined. An integrated model for certain failure modes is proposed. In the materials area, the benefits of soft silicones and so-called magic epoxes are presented.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126949819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.362984
J. Hiatt
This paper presents a failure analysis technique which uses cholesteric liquid crystals and polarized light to locate areas of high power dissipation on an integrated circuit. The technique is non-destructive and can be performed in a few minutes using common failure analysis equipment. An example is given involving the analysis of a CMOS latch-up mechanism.
{"title":"A Method of Detecting Hot Spots on Semiconductors using Liquid Crystals","authors":"J. Hiatt","doi":"10.1109/IRPS.1981.362984","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362984","url":null,"abstract":"This paper presents a failure analysis technique which uses cholesteric liquid crystals and polarized light to locate areas of high power dissipation on an integrated circuit. The technique is non-destructive and can be performed in a few minutes using common failure analysis equipment. An example is given involving the analysis of a CMOS latch-up mechanism.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125743373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.362972
J. E. Gunn, Sushil K. Malik, Purabi M. Mazumdar
A method for highly accelerated bias-temperature humidity stress testing is described. This method allows testing in the regime 100°C/175°C and 50% R.H./85% R.H. Experimental results which demonstrate invariance of corrosion failure modes and lognormal sigmas under different high temperature-humidity conditions are presented. Acceleration factors relative to 85°C/81% R.H. and 60°C/81% R.H. stress tests are given.
{"title":"Highly Accelerated Temperature and Humidity Stress Test Technique (HAST)","authors":"J. E. Gunn, Sushil K. Malik, Purabi M. Mazumdar","doi":"10.1109/IRPS.1981.362972","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362972","url":null,"abstract":"A method for highly accelerated bias-temperature humidity stress testing is described. This method allows testing in the regime 100°C/175°C and 50% R.H./85% R.H. Experimental results which demonstrate invariance of corrosion failure modes and lognormal sigmas under different high temperature-humidity conditions are presented. Acceleration factors relative to 85°C/81% R.H. and 60°C/81% R.H. stress tests are given.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131762501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.362992
K. Nikawa
The dependence of electromigration failure-time on line width and current density was studied using Monte Carlo calculations. In constructing the model used here, A total of three factors were considered: the metallurgical properties of the film, the thermal process during failure propagation, and the stress induced mass flow. In the study on line width dependence, median time to failure (t50) was revealed to decrease as line width decreased to about median grain size, and to increase steeply as the line width decreased further, in good agreement with previous experiments. A wide variety of values assigned to an exponential factor (n) in current density dependence of t50 (t50¿ J-n) was successfully explained by introducing the effective length where a stress gradient has built up.
{"title":"Monte Carlo Calculations Based on the Generalized Electromigration Failure Model","authors":"K. Nikawa","doi":"10.1109/IRPS.1981.362992","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362992","url":null,"abstract":"The dependence of electromigration failure-time on line width and current density was studied using Monte Carlo calculations. In constructing the model used here, A total of three factors were considered: the metallurgical properties of the film, the thermal process during failure propagation, and the stress induced mass flow. In the study on line width dependence, median time to failure (t50) was revealed to decrease as line width decreased to about median grain size, and to increase steeply as the line width decreased further, in good agreement with previous experiments. A wide variety of values assigned to an exponential factor (n) in current density dependence of t50 (t50¿ J-n) was successfully explained by introducing the effective length where a stress gradient has built up.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129624043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.362971
M. L. White, J. Serpiello, K. Striny, W. Rosenzweig
Alpha particle sensitive static RAMs have been shielded from externally emitted radiation with a coating of silicone RTV (Room Temperature Vulcanizing) rubber. This material, which was determined to have an average alpha activity of .0010 cm¿2hr¿1 in the 2-8 Mev range is applied to chips in a hermetic package. The RTV rubber does not affect the sealing yield or reliability of the packages. Devices with this coating were operated error-free for 106 device hours.
{"title":"The use of Silicone RTV Rubber for Alpha Particle Protection on Silicon Integrated Circuits","authors":"M. L. White, J. Serpiello, K. Striny, W. Rosenzweig","doi":"10.1109/IRPS.1981.362971","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362971","url":null,"abstract":"Alpha particle sensitive static RAMs have been shielded from externally emitted radiation with a coating of silicone RTV (Room Temperature Vulcanizing) rubber. This material, which was determined to have an average alpha activity of .0010 cm¿2hr¿1 in the 2-8 Mev range is applied to chips in a hermetic package. The RTV rubber does not affect the sealing yield or reliability of the packages. Devices with this coating were operated error-free for 106 device hours.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123568550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.362970
C. Hsieh, P. Murley, R. R. O'Brien
We studied the transient characteristics of charge collection from alpha-particle tracks in silicon devices. We have run computer calculations using the finite element method, in parallel with experimental work. When an alpha particle penetrates a pn-junction, the generated carriers drastically distort the junction field. After alpha particle penetration, the field, which was originally limited to the depletion region, extends far down into the bulk silicon along the length of the alpha-particle track and funnels a large number of carriers into the struck junction. After less than one nanosecond, the field recovers to its position in the normal depletion layer, and, if the track is long enough, a residue of carriers is left to be transported by diffusion. The extent of this field funneling is a function of substrate concentration, bias voltage, and the alpha-particle energy.
{"title":"Dynamics of Charge Collection from Alpha-Particle Tracks in Integrated Circuits","authors":"C. Hsieh, P. Murley, R. R. O'Brien","doi":"10.1109/IRPS.1981.362970","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362970","url":null,"abstract":"We studied the transient characteristics of charge collection from alpha-particle tracks in silicon devices. We have run computer calculations using the finite element method, in parallel with experimental work. When an alpha particle penetrates a pn-junction, the generated carriers drastically distort the junction field. After alpha particle penetration, the field, which was originally limited to the depletion region, extends far down into the bulk silicon along the length of the alpha-particle track and funnels a large number of carriers into the struck junction. After less than one nanosecond, the field recovers to its position in the normal depletion layer, and, if the track is long enough, a residue of carriers is left to be transported by diffusion. The extent of this field funneling is a function of substrate concentration, bias voltage, and the alpha-particle energy.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126407816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.362965
B. Euzent, N. Boruta, J. Lee, C. Jenq
This paper has discussed a number of E2PROM failure mechanisms for both erase/write cycling and data retention. It has been shown that Fowler-Nordheim tunneling used for programming does not affect data retention. Erase/write cycling has been shown to degrade device margins by only a small amount and is easily guardbanded. Erase/write cycling does contribute to a significant portion of the observed failure rate due to oxide breakdown under high field operation. Defect related charge loss has been shown to be similar to that observed in EPROMs. Finally, it has been shown that E2PROMs can perform reliably in applications requiring up to 10,000 erase/write cycles per byte.
{"title":"Reliability Aspects of a Floating Gate E2 PROM","authors":"B. Euzent, N. Boruta, J. Lee, C. Jenq","doi":"10.1109/IRPS.1981.362965","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362965","url":null,"abstract":"This paper has discussed a number of E2PROM failure mechanisms for both erase/write cycling and data retention. It has been shown that Fowler-Nordheim tunneling used for programming does not affect data retention. Erase/write cycling has been shown to degrade device margins by only a small amount and is easily guardbanded. Erase/write cycling does contribute to a significant portion of the observed failure rate due to oxide breakdown under high field operation. Defect related charge loss has been shown to be similar to that observed in EPROMs. Finally, it has been shown that E2PROMs can perform reliably in applications requiring up to 10,000 erase/write cycles per byte.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127627839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.363003
J. Jaspal, H. Dalal
To achieve the desired Cr-Cr202/Al-Cu laminate chip metalization, first Cr is deposited with the evaporation chamber back-filled with water vapor to a partial pressure of 1 to 4 × 10¿3 Pa. This is followed by standard Al Cu evaporation, lift-off or subetch, sinter, and insulation processing. The critical process step of bleeding in water vapor during Cr evaporation has to be maintained at an optimum because too much Cr202 will lead to high contact resistance and too little Cr202 will lead to a loss of diffusion barrier effectiveness. It is during the sintering cycle that 'Cr' diffusion into the Al-Cu metallization structure occurs along with formation of limited amounts of Al2O03 TThe presence of Al and Cr oxides in turn limits the formation of Cr and Al intermetallics. This results in an acceptable sheet resistance of the metallization structure. Accelerated testing of interconnecting stripes and various sizes of metal contacts to resistor and transistor devices at different temperature and current levels has been completed. As for Al-Cu metallization test results for Cr-Cr203/Al-Cu can be represented by tf J¿n exp(¿H ÷ kT) where J is the current density, T is the temperature, k is the Boltzman constant, ¿H is the activation energy and n is the current exponent. Thus at constant temperature J2 = J1 × (tf1 ÷ tf2)1/n and since for Cr-Cr203/Al-Cu metallurgy the testing done supports an improvement in electromigration lifetime of 1OX, an activation energy of 0.
{"title":"A Three-Fold Increase in Current Carrying Capability of Al-Cu Metallurgy by Pre-Depositing a Suitable Underlay Material","authors":"J. Jaspal, H. Dalal","doi":"10.1109/IRPS.1981.363003","DOIUrl":"https://doi.org/10.1109/IRPS.1981.363003","url":null,"abstract":"To achieve the desired Cr-Cr202/Al-Cu laminate chip metalization, first Cr is deposited with the evaporation chamber back-filled with water vapor to a partial pressure of 1 to 4 × 10¿3 Pa. This is followed by standard Al Cu evaporation, lift-off or subetch, sinter, and insulation processing. The critical process step of bleeding in water vapor during Cr evaporation has to be maintained at an optimum because too much Cr202 will lead to high contact resistance and too little Cr202 will lead to a loss of diffusion barrier effectiveness. It is during the sintering cycle that 'Cr' diffusion into the Al-Cu metallization structure occurs along with formation of limited amounts of Al2O03 TThe presence of Al and Cr oxides in turn limits the formation of Cr and Al intermetallics. This results in an acceptable sheet resistance of the metallization structure. Accelerated testing of interconnecting stripes and various sizes of metal contacts to resistor and transistor devices at different temperature and current levels has been completed. As for Al-Cu metallization test results for Cr-Cr203/Al-Cu can be represented by tf J¿n exp(¿H ÷ kT) where J is the current density, T is the temperature, k is the Boltzman constant, ¿H is the activation energy and n is the current exponent. Thus at constant temperature J2 = J1 × (tf1 ÷ tf2)1/n and since for Cr-Cr203/Al-Cu metallurgy the testing done supports an improvement in electromigration lifetime of 1OX, an activation energy of 0.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130758303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.363006
S. Zalar
Uncoated, SiO2-coated, and polyimide-coated NPN discrete bipolar transistors were subjected to forward life stressing at temperatures between 100°C and 200°C, and at stress current densities in metal lines between 0.2 and 0.8 × 106 A/cm2. The changes of current gain (beta) in these transistors were monitored as the function of stress time up to 1000 hours. Beta degradation in uncoated transistors started immediately. Later, however, when the mechanical stress generated by electromigration reached the yield point of CrAlCu metallurgy in the emitter area, the beta showed a strong recovery to values about 10% higher than the beta at time zero. This explanation was corroborated by the observation of extrusions in the scanning electron microscope. The overlayer of 2.4 ¿m of sputtered SiO2 strongly retarded the beginning of beta degradation but did not prevent it toward the end of life stressing. The overlayer of 2.7 ¿m of spun-on polyimide initially had a negligible effect on the beginning of beta degradation. Later, however, when the yield point of metallurgy was achieved, the polyimide seemed to partially block the extrusion of hillocks and prevented the recovery of beta. This was confirmed by SEM photography. The experiment verified the basic premise that the forward beta degradation in bipolar transistors can be described in terms of the mechanical stress generated by electromigration in the emitter region.
{"title":"The Effect of Insulation Coatings on Forward Beta Degradation in Bipolar Transistors","authors":"S. Zalar","doi":"10.1109/IRPS.1981.363006","DOIUrl":"https://doi.org/10.1109/IRPS.1981.363006","url":null,"abstract":"Uncoated, SiO2-coated, and polyimide-coated NPN discrete bipolar transistors were subjected to forward life stressing at temperatures between 100°C and 200°C, and at stress current densities in metal lines between 0.2 and 0.8 × 106 A/cm2. The changes of current gain (beta) in these transistors were monitored as the function of stress time up to 1000 hours. Beta degradation in uncoated transistors started immediately. Later, however, when the mechanical stress generated by electromigration reached the yield point of CrAlCu metallurgy in the emitter area, the beta showed a strong recovery to values about 10% higher than the beta at time zero. This explanation was corroborated by the observation of extrusions in the scanning electron microscope. The overlayer of 2.4 ¿m of sputtered SiO2 strongly retarded the beginning of beta degradation but did not prevent it toward the end of life stressing. The overlayer of 2.7 ¿m of spun-on polyimide initially had a negligible effect on the beginning of beta degradation. Later, however, when the yield point of metallurgy was achieved, the polyimide seemed to partially block the extrusion of hillocks and prevented the recovery of beta. This was confirmed by SEM photography. The experiment verified the basic premise that the forward beta degradation in bipolar transistors can be described in terms of the mechanical stress generated by electromigration in the emitter region.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117179599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.362983
C. Zipfel, A. Chin, V. Keramidas, R. H. Saul
Double heterostructure Gal-xAlXAs LEDs operated at high current densities (3 × 103 A/cm2) are being used as sources in lightwave communication systems, for example in optical data links. This paper discusses the reliability of these devices, distinguishing between catastrophic degradation due to Dark Line Defect (DLD) formation and gradual aging mechanisms. Two modes of DLD formation are observed: (1) A certain percentage of devices fail in relatively short times by DLD formation at threading dislocations. The growth of these DLDs is strongly current dependent, but independent of temperature. A 100h, 100 mA burn-in eliminates all of the devices which fail by this mode. Burn-in failures can be kept as low as 5%. (2) Under accelerated aging as many as 25% of the devices which passed the burn-in fail after 103h by a new mode of DLD formation. This mode is temperature dependent and related to stress at the dielectric-metal interface. Analysis shows that a 25% freak population gives ¿40 FITS at 70°C. Accelerated aging studies of clear devices are complicated by two competing processes: a slow degradation in light output and a slow increase which dominates at high temperatures. Activation energies for the two processes are 0.65 and 0.75 eV, respectively. Projected values of MTTF are 9 × 107h at 25°C and 4 × 106h at 70°C.
{"title":"Reliability of DH Ga1-XAlX As LEDs For Lightwave Communications","authors":"C. Zipfel, A. Chin, V. Keramidas, R. H. Saul","doi":"10.1109/IRPS.1981.362983","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362983","url":null,"abstract":"Double heterostructure Gal-xAlXAs LEDs operated at high current densities (3 × 103 A/cm2) are being used as sources in lightwave communication systems, for example in optical data links. This paper discusses the reliability of these devices, distinguishing between catastrophic degradation due to Dark Line Defect (DLD) formation and gradual aging mechanisms. Two modes of DLD formation are observed: (1) A certain percentage of devices fail in relatively short times by DLD formation at threading dislocations. The growth of these DLDs is strongly current dependent, but independent of temperature. A 100h, 100 mA burn-in eliminates all of the devices which fail by this mode. Burn-in failures can be kept as low as 5%. (2) Under accelerated aging as many as 25% of the devices which passed the burn-in fail after 103h by a new mode of DLD formation. This mode is temperature dependent and related to stress at the dielectric-metal interface. Analysis shows that a 25% freak population gives ¿40 FITS at 70°C. Accelerated aging studies of clear devices are complicated by two competing processes: a slow degradation in light output and a slow increase which dominates at high temperatures. Activation energies for the two processes are 0.65 and 0.75 eV, respectively. Projected values of MTTF are 9 × 107h at 25°C and 4 × 106h at 70°C.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124570535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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