基于DFG模型的低功耗结构设计方法

2010 5th IEEE Conference on Industrial Electronics and Applications Pub Date : 2010-06-15 DOI:10.1109/ICIEA.2010.5515249

Tingting Chen, Zheying Li

{"title":"基于DFG模型的低功耗结构设计方法","authors":"Tingting Chen, Zheying Li","doi":"10.1109/ICIEA.2010.5515249","DOIUrl":null,"url":null,"abstract":"A low power architecture design method is brought forward by this paper based on DFG (Data Flow Graphic) model. Through this method, a DFG model is extracted from the logic model of a circuit or a system and is used to optimize the circuit architecture for reducing the power consumption of circuit. In this paper, the data transmission process of USB2.0 is taken as an example to prove the correctness of this low power architecture design method.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low power architecture design method based on DFG model\",\"authors\":\"Tingting Chen, Zheying Li\",\"doi\":\"10.1109/ICIEA.2010.5515249\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low power architecture design method is brought forward by this paper based on DFG (Data Flow Graphic) model. Through this method, a DFG model is extracted from the logic model of a circuit or a system and is used to optimize the circuit architecture for reducing the power consumption of circuit. In this paper, the data transmission process of USB2.0 is taken as an example to prove the correctness of this low power architecture design method.\",\"PeriodicalId\":234296,\"journal\":{\"name\":\"2010 5th IEEE Conference on Industrial Electronics and Applications\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 5th IEEE Conference on Industrial Electronics and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIEA.2010.5515249\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 5th IEEE Conference on Industrial Electronics and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIEA.2010.5515249","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

提出了一种基于DFG(数据流图)模型的低功耗架构设计方法。通过该方法，从电路或系统的逻辑模型中提取DFG模型，并用于优化电路结构，以降低电路的功耗。本文以USB2.0的数据传输过程为例，验证了这种低功耗架构设计方法的正确性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A low power architecture design method based on DFG model

A low power architecture design method is brought forward by this paper based on DFG (Data Flow Graphic) model. Through this method, a DFG model is extracted from the logic model of a circuit or a system and is used to optimize the circuit architecture for reducing the power consumption of circuit. In this paper, the data transmission process of USB2.0 is taken as an example to prove the correctness of this low power architecture design method.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2010 5th IEEE Conference on Industrial Electronics and Applications

自引率

0.00%

发文量