Pub Date : 2010-07-23DOI: 10.1109/ICIEA.2010.5517100
Jia Zhao, Wei Zhang, Jin Fang, Zhongping Yang, T. Zheng, Youmei Liu
This paper presents the application of Genetic Algorithm (GA) and the Finite Element Method (FEM) for optimal design of a High Temperature Superconducting Linear Induction Motor (HTS LIM). The design procedure is much different from that of traditional Linear Induction Motors (LIMs). First, the GA method is used to produce a series of optimal design data. The product of efficiency and power factor is taken as an objective function in order to maximize the product under a constant current drive; second, due to the new and unique structure the model of the motor using the optimal data should be analyzed with the finite element method in order to confirm the accuracy of the model. As a result, it is known that the novel method is very accurate as an HTS LIM optimization technique.
{"title":"Design of HTS Linear Induction Motor using GA and the Finite Element Method","authors":"Jia Zhao, Wei Zhang, Jin Fang, Zhongping Yang, T. Zheng, Youmei Liu","doi":"10.1109/ICIEA.2010.5517100","DOIUrl":"https://doi.org/10.1109/ICIEA.2010.5517100","url":null,"abstract":"This paper presents the application of Genetic Algorithm (GA) and the Finite Element Method (FEM) for optimal design of a High Temperature Superconducting Linear Induction Motor (HTS LIM). The design procedure is much different from that of traditional Linear Induction Motors (LIMs). First, the GA method is used to produce a series of optimal design data. The product of efficiency and power factor is taken as an objective function in order to maximize the product under a constant current drive; second, due to the new and unique structure the model of the motor using the optimal data should be analyzed with the finite element method in order to confirm the accuracy of the model. As a result, it is known that the novel method is very accurate as an HTS LIM optimization technique.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133057048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-23DOI: 10.1109/ICIEA.2010.5515281
Jian-hang Zhang, Jingyue Wang, Rui Wang, G. Hou
Next-day electricity prices forecasting is essential to consumers and producers. Due to the stochastic characteristics of the electricity price time series, a novel model of electricity price forecasting is presented based on the Hidden Markov Model (HMM). The factors impacting the electricity price forecasting are discussed. The proposed approach is utilized in an electricity market, the results show the effectiveness.
{"title":"Forecasting next-day electricity prices with Hidden Markov Models","authors":"Jian-hang Zhang, Jingyue Wang, Rui Wang, G. Hou","doi":"10.1109/ICIEA.2010.5515281","DOIUrl":"https://doi.org/10.1109/ICIEA.2010.5515281","url":null,"abstract":"Next-day electricity prices forecasting is essential to consumers and producers. Due to the stochastic characteristics of the electricity price time series, a novel model of electricity price forecasting is presented based on the Hidden Markov Model (HMM). The factors impacting the electricity price forecasting are discussed. The proposed approach is utilized in an electricity market, the results show the effectiveness.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130840395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/IPEC.2010.5544586
Chih‐Hong Lin, Poh Chiang, Chi-Shin Tseng, Yi-Ling Liu, Mei-Yu Lee
The purpose of this paper is to investigate and implement a novel approach to learning control for permanent magnet synchronous motor (PMSM) drive system using a hybrid recurrent fuzzy neural network (HRFNN) control. First, the field-oriented mechanism is applied to formulate the dynamic equation of the PMSM servo drive. Then, a HRFNN speed control system that combined supervisor control, RFNN and compensated control is developed to control PMSM drive system. Finally, the effectiveness of the proposed control scheme is verified by the experimental results.
{"title":"Hybrid recurrent fuzzy neural network control for permanent magnet synchronous motor applied in electric scooter","authors":"Chih‐Hong Lin, Poh Chiang, Chi-Shin Tseng, Yi-Ling Liu, Mei-Yu Lee","doi":"10.1109/IPEC.2010.5544586","DOIUrl":"https://doi.org/10.1109/IPEC.2010.5544586","url":null,"abstract":"The purpose of this paper is to investigate and implement a novel approach to learning control for permanent magnet synchronous motor (PMSM) drive system using a hybrid recurrent fuzzy neural network (HRFNN) control. First, the field-oriented mechanism is applied to formulate the dynamic equation of the PMSM servo drive. Then, a HRFNN speed control system that combined supervisor control, RFNN and compensated control is developed to control PMSM drive system. Finally, the effectiveness of the proposed control scheme is verified by the experimental results.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121241670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/ICIEA.2010.5515886
Sheng-Yuan Ou, Huei-Fa Su, Ho-Pu Hsiao
A novel modulation control scheme of switching frequency for multiphase synchronous rectified voltage regulator module (VRM) used in such as motherboards is proposed in this paper. The switching frequency is modulated higher as VRM loads more lightly and vice versa, so that the proposed scheme is also called variable-frequency control method. Zero voltage switching (ZVS) can be achieved to boost VRM efficiency without additional auxiliary switches and any storage elements while frequency is modulated. To protect elements in VRM from damage and cause the output ripple under control and in view of the switching frequency being finite, the switching frequency will be fixed constant when the much more loading is added on VRM wherein the load threshold to fix switching frequency constant is found by experiments. Compared to conventional constant switching frequency techniques with 250kHz and 550kHz, experimental results derived from an eight-phase synchronous rectified VRM show the proposed modulation technique is superior to the conventional one, the efficiency can be increased up to 8% for eight-phase VRM under various load conditions.
{"title":"A novel variable frequency modulation technique for multiphase synchronous rectified VRM","authors":"Sheng-Yuan Ou, Huei-Fa Su, Ho-Pu Hsiao","doi":"10.1109/ICIEA.2010.5515886","DOIUrl":"https://doi.org/10.1109/ICIEA.2010.5515886","url":null,"abstract":"A novel modulation control scheme of switching frequency for multiphase synchronous rectified voltage regulator module (VRM) used in such as motherboards is proposed in this paper. The switching frequency is modulated higher as VRM loads more lightly and vice versa, so that the proposed scheme is also called variable-frequency control method. Zero voltage switching (ZVS) can be achieved to boost VRM efficiency without additional auxiliary switches and any storage elements while frequency is modulated. To protect elements in VRM from damage and cause the output ripple under control and in view of the switching frequency being finite, the switching frequency will be fixed constant when the much more loading is added on VRM wherein the load threshold to fix switching frequency constant is found by experiments. Compared to conventional constant switching frequency techniques with 250kHz and 550kHz, experimental results derived from an eight-phase synchronous rectified VRM show the proposed modulation technique is superior to the conventional one, the efficiency can be increased up to 8% for eight-phase VRM under various load conditions.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115237397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/ICIEA.2010.5515093
Zhang Ya-jing, Gao Ji-lei, Lin Fei, T. Zheng, Li Hong, He Ming-zhi
Accurate and fast grid voltage detection is critical for four quadrant converters of high speed train. The weighted least-square estimation method (WLSE) is used in this paper. This method is able to measure instantaneously the fundamental component, the phase angle and the frequency of the line voltage without a significant delay (in a few sampling periods). Three schemes of phase angle estimation including zero crossing detector, PLL and WLSE are analyzed and compared in detail. The simulations and experiment show that WLSE has the best performance under distorted and transient grid conditions.
{"title":"Performance analysis and comparison of phase angle estimation schemes for four-quadrant converters of high speed train","authors":"Zhang Ya-jing, Gao Ji-lei, Lin Fei, T. Zheng, Li Hong, He Ming-zhi","doi":"10.1109/ICIEA.2010.5515093","DOIUrl":"https://doi.org/10.1109/ICIEA.2010.5515093","url":null,"abstract":"Accurate and fast grid voltage detection is critical for four quadrant converters of high speed train. The weighted least-square estimation method (WLSE) is used in this paper. This method is able to measure instantaneously the fundamental component, the phase angle and the frequency of the line voltage without a significant delay (in a few sampling periods). Three schemes of phase angle estimation including zero crossing detector, PLL and WLSE are analyzed and compared in detail. The simulations and experiment show that WLSE has the best performance under distorted and transient grid conditions.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123084478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/ICIEA.2010.5516956
Ya-Gang Wang, Xiao-Ming Xu, W. Cai
This paper presents a new technique of adaptive PI controller for large dead-time processes with sensitivity specification. On the basis of process input and output data of normal operation in the control loop, the important frequency responses of process are estimated with signal decomposition and Laplace analysis, and then a first-order plus dead-time model is identified for large dead-time processes. Finally PI control parameters are calculated to satisfy sensitivity specification. The adaptive procedure of PI controller does not need any prior knowledge of the process and previous controller while the control loop is still in the normal operation. Simulation examples are given to show both effectiveness and feasibility of the adaptive PI controller.
{"title":"Robust adaptive PI controllers for large dead-time processes with sensitivity specification","authors":"Ya-Gang Wang, Xiao-Ming Xu, W. Cai","doi":"10.1109/ICIEA.2010.5516956","DOIUrl":"https://doi.org/10.1109/ICIEA.2010.5516956","url":null,"abstract":"This paper presents a new technique of adaptive PI controller for large dead-time processes with sensitivity specification. On the basis of process input and output data of normal operation in the control loop, the important frequency responses of process are estimated with signal decomposition and Laplace analysis, and then a first-order plus dead-time model is identified for large dead-time processes. Finally PI control parameters are calculated to satisfy sensitivity specification. The adaptive procedure of PI controller does not need any prior knowledge of the process and previous controller while the control loop is still in the normal operation. Simulation examples are given to show both effectiveness and feasibility of the adaptive PI controller.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117225676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/ICIEA.2010.5515678
Mu Jian-guo, Wang Li, H. Jie
Concerning the problems of topologies in current patents, the improvements to the structure of solid-state circuit breakers are made to enhance the reliability and to broaden the field of application and to reduce the manufacturing costs. A novel circuit breaker topology is proposed in this paper, which is improved by using the current-commutation of hybrid circuit breakers for reference. By making use of soft-switching and current-commutation forced by resonance, the new topology can not only successfully realize the soft turn-on and fast turn-off but also can be applied in the situation of higher voltage level. The topology is presented and mathematical model is built by mode analysis. Finally, the normal turn-on and turn-off experiment was taken on a prototype. The experimental results show the feasibility of the proposed topology and verify the correctness of theoretical derivations.
{"title":"Research on main circuit topology for a novel DC solid-state circuit breaker","authors":"Mu Jian-guo, Wang Li, H. Jie","doi":"10.1109/ICIEA.2010.5515678","DOIUrl":"https://doi.org/10.1109/ICIEA.2010.5515678","url":null,"abstract":"Concerning the problems of topologies in current patents, the improvements to the structure of solid-state circuit breakers are made to enhance the reliability and to broaden the field of application and to reduce the manufacturing costs. A novel circuit breaker topology is proposed in this paper, which is improved by using the current-commutation of hybrid circuit breakers for reference. By making use of soft-switching and current-commutation forced by resonance, the new topology can not only successfully realize the soft turn-on and fast turn-off but also can be applied in the situation of higher voltage level. The topology is presented and mathematical model is built by mode analysis. Finally, the normal turn-on and turn-off experiment was taken on a prototype. The experimental results show the feasibility of the proposed topology and verify the correctness of theoretical derivations.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"29 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121012657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/ICIEA.2010.5514708
Te Li, R. Yu, H. Shu, S. Rahardja
The paper proposes a fixed quality layered bitstream truncator based on the MPEG-4 scalable lossless (SLS) audio coding system where, in contrast to original SLS truncator, the bitrate for each audio frame after truncation is not constant but instead an attempt is made to create constant quality audio. With the bitrate constraint for a period, the proposed system truncates each audio frame according to a pre-trained bitrate table. Simulation results show that with the same bandwidth, a constant and enhanced quality can be achieved by using the proposed method comparing with the one using the traditional fixed bitrate truncation method.
{"title":"Fixed quality layered truncation for scalable lossless audio","authors":"Te Li, R. Yu, H. Shu, S. Rahardja","doi":"10.1109/ICIEA.2010.5514708","DOIUrl":"https://doi.org/10.1109/ICIEA.2010.5514708","url":null,"abstract":"The paper proposes a fixed quality layered bitstream truncator based on the MPEG-4 scalable lossless (SLS) audio coding system where, in contrast to original SLS truncator, the bitrate for each audio frame after truncation is not constant but instead an attempt is made to create constant quality audio. With the bitrate constraint for a period, the proposed system truncates each audio frame according to a pre-trained bitrate table. Simulation results show that with the same bandwidth, a constant and enhanced quality can be achieved by using the proposed method comparing with the one using the traditional fixed bitrate truncation method.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124928580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/ICIEA.2010.5515257
W. Gao, D. Gao, C. Hu-Guo, T. Wei, Yann Hu
This paper presents a novel digital delay-locked loop (DDLL) dedicated to generate multiphase delayed clocks for the development of the multi-channel analog-to-digital converters (ADCs) and/or time-to-digital converters (TDCs). The DDLL consists of a digital delay chain using linear delay elements, a Bangbang phase detector, a Up/Down counter and a digital filter. The digital filter is utilized to reduce digital ripples when DDLL is locked. A prototype chip of the proposed DDLL with 32 delay cells is designed and fabricated in AMS 0.35 µm CMOS process. The die area is 690 µm × 73 µm. For the DDLL core, the rms jitter and the peak-to-peak jitter of is 0 and 19.8 ps at 50 MHz clock. However, jitter-tolerant performances can be achieved when the DDLL core and the digital filter are used as a multiphase clock generator. The total power dissipation is about 3 mW.
{"title":"A low-jitter multiphase digital delay-locked loop for nuclear instruments and biomedical imaging applications","authors":"W. Gao, D. Gao, C. Hu-Guo, T. Wei, Yann Hu","doi":"10.1109/ICIEA.2010.5515257","DOIUrl":"https://doi.org/10.1109/ICIEA.2010.5515257","url":null,"abstract":"This paper presents a novel digital delay-locked loop (DDLL) dedicated to generate multiphase delayed clocks for the development of the multi-channel analog-to-digital converters (ADCs) and/or time-to-digital converters (TDCs). The DDLL consists of a digital delay chain using linear delay elements, a Bangbang phase detector, a Up/Down counter and a digital filter. The digital filter is utilized to reduce digital ripples when DDLL is locked. A prototype chip of the proposed DDLL with 32 delay cells is designed and fabricated in AMS 0.35 µm CMOS process. The die area is 690 µm × 73 µm. For the DDLL core, the rms jitter and the peak-to-peak jitter of is 0 and 19.8 ps at 50 MHz clock. However, jitter-tolerant performances can be achieved when the DDLL core and the digital filter are used as a multiphase clock generator. The total power dissipation is about 3 mW.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124997623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/ICIEA.2010.5517124
R. Hong, G. Chang, C. Chao, Y. Chu, C. I. Chen
This paper presents an approach of incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter (APF) design. Even when the three-phase source voltages are unbalanced and/or distorted and supply to a nonlinear load, the described compensation strategy can compensate the harmonic and neutral current, and thus improve the power factor. After verifying the efficiency of compensation strategy, the APF control strategy is embedded into the digital signal processor (DSP) to verify the feasibility of the proposed strategy on hardware in the loop (HIL) structure. Results show that the proposed approach is effective for shunt APF design.
{"title":"Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design","authors":"R. Hong, G. Chang, C. Chao, Y. Chu, C. I. Chen","doi":"10.1109/ICIEA.2010.5517124","DOIUrl":"https://doi.org/10.1109/ICIEA.2010.5517124","url":null,"abstract":"This paper presents an approach of incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter (APF) design. Even when the three-phase source voltages are unbalanced and/or distorted and supply to a nonlinear load, the described compensation strategy can compensate the harmonic and neutral current, and thus improve the power factor. After verifying the efficiency of compensation strategy, the APF control strategy is embedded into the digital signal processor (DSP) to verify the feasibility of the proposed strategy on hardware in the loop (HIL) structure. Results show that the proposed approach is effective for shunt APF design.","PeriodicalId":234296,"journal":{"name":"2010 5th IEEE Conference on Industrial Electronics and Applications","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125820782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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