C. Lee, S. Mochizuki, R. Southwick, J. Li, Xin He Miao, R. Bao, T. Ando, R. Galatage, S. Siddiqui, C. Labelle, A. Knorr, J. Stathis, D. Guo, V. Narayanan, B. Haran, H. Jagannathan
{"title":"利用平面fet、finfet和应变松弛缓冲层finfet对Si1−xGex沟道中的应变和Ge含量进行了比较研究","authors":"C. Lee, S. Mochizuki, R. Southwick, J. Li, Xin He Miao, R. Bao, T. Ando, R. Galatage, S. Siddiqui, C. Labelle, A. Knorr, J. Stathis, D. Guo, V. Narayanan, B. Haran, H. Jagannathan","doi":"10.1109/IEDM.2017.8268509","DOIUrl":null,"url":null,"abstract":"Strained Si<inf>1−x</inf> Ge<inf>x</inf> channel pFinFETs and planar pFETs are fabricated on a strain relaxed buffer virtual substrate to comparatively study the electrical impact of strain and Ge content in the Si<inf>1−x</inf>Ge<inf>x</inf> channel. By comparing the transistor electrical properties of Si<inf>1−x</inf>Ge<inf>x</inf> pFETs on SRB with Si<inf>1−x</inf>Ge<inf>x</inf> pFETs on Si substrate, we successfully decouple the influence of strain and Ge content in the Si<inf>1−x</inf> Ge<inf>x</inf> channel on device performance such as gate stack quality, reliability, and carrier transport. Based on these understandings, dual channel Si/Si<inf>1−x</inf>Ge<inf>x</inf> FinFETs on the SRB with the optimized surface orientation is proposed to further improve the device performance.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"A comparative study of strain and Ge content in Si1−xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs\",\"authors\":\"C. Lee, S. Mochizuki, R. Southwick, J. Li, Xin He Miao, R. Bao, T. Ando, R. Galatage, S. Siddiqui, C. Labelle, A. Knorr, J. Stathis, D. Guo, V. Narayanan, B. Haran, H. Jagannathan\",\"doi\":\"10.1109/IEDM.2017.8268509\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Strained Si<inf>1−x</inf> Ge<inf>x</inf> channel pFinFETs and planar pFETs are fabricated on a strain relaxed buffer virtual substrate to comparatively study the electrical impact of strain and Ge content in the Si<inf>1−x</inf>Ge<inf>x</inf> channel. By comparing the transistor electrical properties of Si<inf>1−x</inf>Ge<inf>x</inf> pFETs on SRB with Si<inf>1−x</inf>Ge<inf>x</inf> pFETs on Si substrate, we successfully decouple the influence of strain and Ge content in the Si<inf>1−x</inf> Ge<inf>x</inf> channel on device performance such as gate stack quality, reliability, and carrier transport. Based on these understandings, dual channel Si/Si<inf>1−x</inf>Ge<inf>x</inf> FinFETs on the SRB with the optimized surface orientation is proposed to further improve the device performance.\",\"PeriodicalId\":412333,\"journal\":{\"name\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2017.8268509\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268509","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A comparative study of strain and Ge content in Si1−xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs
Strained Si1−x Gex channel pFinFETs and planar pFETs are fabricated on a strain relaxed buffer virtual substrate to comparatively study the electrical impact of strain and Ge content in the Si1−xGex channel. By comparing the transistor electrical properties of Si1−xGex pFETs on SRB with Si1−xGex pFETs on Si substrate, we successfully decouple the influence of strain and Ge content in the Si1−x Gex channel on device performance such as gate stack quality, reliability, and carrier transport. Based on these understandings, dual channel Si/Si1−xGex FinFETs on the SRB with the optimized surface orientation is proposed to further improve the device performance.