Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing

We present a Hardware Trojan (HT) detection, identification and recovery mechanism for Multiprocessor Systems on Chips (MPSoCs). Our method utilizes on-line testing to mitigate the effects of hardware Trojans in a computing system using a Hardware Security Monitor (HSM), a trusted hardware module, and an On-line Test Procedure (OTP), a software module. The proposed approach focuses on mitigating hardware Trojans with a permanent impact on the computing system and enables MPSoCs to continue functioning in the presence of the hardware Trojans. We have successfully validated the proposed method by implementing known hardware Trojans from Trust-Hub on a Xilinx ML605 FPGA. The implementation incurred 4.5% area and 9.1% execution time overheads for a set of benchmark applications. Compared to the state of the art, the proposed mechanism’s area and power overheads are significantly lower while the execution time overhead is slightly higher. State of the art systems utilizing differing cores have been shown to be effective in simulation environments, while the proposed mechanism has been implemented in FPGAs to illustrate that such a system can be realized in hardware.