低功率并行乘法器

VLSI Signal Processing, IX Pub Date : 1996-10-30 DOI:10.1109/VLSISP.1996.558332

Edwin de Angel, Earl E. Swartzlander

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引用次数: 58

摘要

本文介绍并比较了用于减少开关活动和提高并行乘法器性能的符号扩展技术。对不同的符号扩展方案进行了详细的回顾，并提出了一种降低功耗的改进方案。采用4个以0.6 /spl mu/m技术设计的并行CMOS乘法器来实现和比较符号扩展方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low power parallel multipliers

This paper presents and compares sign extension techniques used to decrease the switching activity and improve the performance of parallel multipliers. A detailed review of different sign extension schemes is presented and an improved scheme for reducing the power dissipation is proposed. Four parallel CMOS multipliers designed in 0.6 /spl mu/m technology are used to implement and compare the sign extension schemes.

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VLSI Signal Processing, IX

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