Rafael N. M. Oliveira, F. A. D. Silva, Ricardo Reis, C. Meinhardt
{"title":"7纳米FinFET技术镜面全加法器的SET缓解技术","authors":"Rafael N. M. Oliveira, F. A. D. Silva, Ricardo Reis, C. Meinhardt","doi":"10.1109/LATS53581.2021.9651889","DOIUrl":null,"url":null,"abstract":"This paper presents a comparative analysis of radiation sensitivity and SET mitigation techniques for the Mirror Full Adder topology implemented with FinFET devices at 7 nm node, considering nominal and near-threshold operation. The mitigation techniques investigated are Decoupling Cells and Transistor Sizing. Transistor Sizing may improved robustness up to $2\\mathrm{x}$ (nominal) and close to $3\\mathrm{x}$ (near-threshold). Combining the techniques decreases the total error occurrence close to 60% at nominal operation and up to 34% at near-threshold operation.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology\",\"authors\":\"Rafael N. M. Oliveira, F. A. D. Silva, Ricardo Reis, C. Meinhardt\",\"doi\":\"10.1109/LATS53581.2021.9651889\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a comparative analysis of radiation sensitivity and SET mitigation techniques for the Mirror Full Adder topology implemented with FinFET devices at 7 nm node, considering nominal and near-threshold operation. The mitigation techniques investigated are Decoupling Cells and Transistor Sizing. Transistor Sizing may improved robustness up to $2\\\\mathrm{x}$ (nominal) and close to $3\\\\mathrm{x}$ (near-threshold). Combining the techniques decreases the total error occurrence close to 60% at nominal operation and up to 34% at near-threshold operation.\",\"PeriodicalId\":404536,\"journal\":{\"name\":\"2021 IEEE 22nd Latin American Test Symposium (LATS)\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 22nd Latin American Test Symposium (LATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LATS53581.2021.9651889\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 22nd Latin American Test Symposium (LATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LATS53581.2021.9651889","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology
This paper presents a comparative analysis of radiation sensitivity and SET mitigation techniques for the Mirror Full Adder topology implemented with FinFET devices at 7 nm node, considering nominal and near-threshold operation. The mitigation techniques investigated are Decoupling Cells and Transistor Sizing. Transistor Sizing may improved robustness up to $2\mathrm{x}$ (nominal) and close to $3\mathrm{x}$ (near-threshold). Combining the techniques decreases the total error occurrence close to 60% at nominal operation and up to 34% at near-threshold operation.
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