低功耗高速1mb CMOS SRAM

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06) Pub Date : 2006-01-17 DOI:10.1109/DELTA.2006.6

Tan Soon-Hwei, Loh Poh-Yee, M. Sulaiman

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引用次数: 0

摘要

介绍了一种异步双端口1mb CMOS SRAM。SRAM在双端口模式下最大工作频率为220MHz，最小有功功耗为31mW，最小待机功耗为80nW。仿真结果表明，该电路在较宽的工艺、电压和温度(PVT)转角范围内均能正常工作。SRAM采用TSMC CMOS 0.25/spl mu/m 1P5M盐化工艺定制设计，硅面积约为115mm/sup 2/ (11.5mm /spl × 10mm)。

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A low-power high-speed 1-Mb CMOS SRAM

An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of process, voltage & temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25/spl mu/m 1P5M salicide process and occupies a silicon area of approximately 115mm/sup 2/ (11.5mm /spl times/ 10mm).

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Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

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