考虑源极和漏极横向高斯掺杂分布的单材料双栅MOSFET栅极失调效应研究

Himanshu Diwakar, S. Nayak, Rohit Kumar
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引用次数: 1

摘要

在栅极无意的不对准由于制造导致不良的器件性能。本文在仿真的基础上,研究了单材料双栅MOSFET中栅极错位的影响。源极和漏极被认为是横向高斯掺杂。通过仿真研究,分析了栅极错位对器件性能的影响。模拟了四种错位的组合,研究了对表面电位、器件I-V特性和跨导的影响。我们考虑了前后门漏侧和源侧的不对准。当不对准时,跨导电流和漏极电流都减小。漏极和源侧的错位同样降低了跨电导,但当正极错位45%时,漏极电流衰减34.8%,而后门的类似错位导致57.5%的衰减。为了模拟,使用了Silvaco公司的ATLAS™二维模拟,并获得了表面电位剖面。
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Study of Gate Misalignment Effects in Single-Material Double-Gate (SMDG) MOSFET Considering Source and Drain Lateral Gaussian Doping Profile
Un-intentional misalignment in the gate due to fabrication leads to undesirable device performances. In this paper, effect of gate misalignment has been presented in single-material double-gate (SMDG) MOSFET, based on simulation. The source and drain are considered to be doped with lateral Gaussian doping profile. A simulation study is performed to analyze the gate misalignment effects on the performance. A combination of total four misalignment is simulated, the effects on surface potential, device I-V characteristics and transconductance has been studied. We consider the misalignment at drain and source side of both front and back gate. When misalignment is there both trans-conductance and drain current decreases. Misalignment from drain and source side decreases trans-conductance similarly, but for 45% misalignment in the front gate, 34.8% degradation in the drain current is observed while similar misalignment in back gate causes 57.5% degradation. For simulations 2-D simulations by ATLAS™ from Silvaco Inc. is used and surface potential profile is obtained.
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