S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison
{"title":"双N/P-LDMOS晶体管的TCAD优化","authors":"S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison","doi":"10.1109/ESSDERC.2011.6044188","DOIUrl":null,"url":null,"abstract":"The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"TCAD optimization of a dual N/P-LDMOS transistor\",\"authors\":\"S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison\",\"doi\":\"10.1109/ESSDERC.2011.6044188\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.\",\"PeriodicalId\":161896,\"journal\":{\"name\":\"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2011.6044188\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2011.6044188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.