S. Wada, M. Tokushima, M. Fukaishi, N. Matsuno, H. Yano, H. Hida
{"title":"采用化学镀金和准直溅射技术制备的小于0.25/spl mu/m对称超自对准栅极边缘电容","authors":"S. Wada, M. Tokushima, M. Fukaishi, N. Matsuno, H. Yano, H. Hida","doi":"10.1109/DRC.1994.1009449","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"\\\"A sub-0.25/spl mu/m symmetric super self-aligned gate hjfet witn reduced gate fringing capacitance fabricated using electroless au plating and collimated sputtering\\\"\",\"authors\":\"S. Wada, M. Tokushima, M. Fukaishi, N. Matsuno, H. Yano, H. Hida\",\"doi\":\"10.1109/DRC.1994.1009449\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\",\"PeriodicalId\":244069,\"journal\":{\"name\":\"52nd Annual Device Research Conference\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"52nd Annual Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.1994.1009449\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"52nd Annual Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.1994.1009449","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
"A sub-0.25/spl mu/m symmetric super self-aligned gate hjfet witn reduced gate fringing capacitance fabricated using electroless au plating and collimated sputtering"