一个9b 2GS/s 45mW 2x交错ADC

2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI:10.1109/ESSCIRC.2013.6649088

J. Pernillo, M. Flynn

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引用次数: 5

摘要

9b 2GS/s ADC架构将一对两级流水线ADC交织在一起，通过共享的低增益运算放大器和共享的低精度第二级子ADC实现高性能。这种技术减少了面积，消除了对通道间增益和偏置不匹配进行校正的需要。对于以2GS/s采样的1GHz信号输入，ADC的测量ENOB为7.07b，从1.0V电源消耗45mW，产生167fJ/转换步长的FOM。

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A 9b 2GS/s 45mW 2X-interleaved ADC

A 9b 2GS/s ADC architecture interleaves a pair of two-stage pipeline ADCs to achieve high performance with a shared low-gain op-amp and a shared low-accuracy 2nd stage sub-ADC. This technique reduces area and eliminates the need to correct for gain and offset mismatch between channels. The ADC achieves a measured ENOB of 7.07b for a 1GHz signal input sampled at 2GS/s and consumes 45mW from a 1.0V supply, yielding an FOM of 167fJ/conversion-step.

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2013 Proceedings of the ESSCIRC (ESSCIRC)

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