An efficient FPGA-based design for the AVMF filter

This paper introduces an efficient parallel hardware architecture to implement the Adaptive Vector Median Filter (AVMF) in Field Programmable Gate Array (FPGA). This architecture is developed using the VHSIC Hardware Description language (VHDL) language and integrated in the Hardware/Software (HW/SW) environment as coprocessor. The NIOS II softcore processor is used to execute the SW part. The communication between HW and SW parts is carried out through the Avalon bus. The experimental results on the Stratix II development board show that the HW/SW AVMF system allows a reduction in processing time by 572 times relative to the SW solution at 140MHz with small decrease in image quality.