A multiplier-less FPGA core for image algebra neighbourhood operations

This paper presents the design and implementation of a high-level generator of optimised FPGA configurations for Image Algebra (IA) neighbourhood operations. These configurations are parameterised and scaleable in terms of the IA operation itself the window size, the window coefficients, the input pixel word length and the image size. The window coefficients of the neighbourhood operations are represented as sum/subtract of power of twos in Canonical Signed Digit (CSD) representation, which means that the usually costly multiplication operation can be easily implemented using a small number of simple shift-and-add operations, leading to considerable hardware savings. EDIF netlists are generated automatically from high-level descriptions of the IA operations in /spl sim/1 sec. These are specifically optimised for Xilinx XC4000 chips, although implementations for other targets can also be easily realised.