{"title":"基于电荷阱的3D NAND阵列中的分布式循环:模型和资格测试含义","authors":"G. Nicosia, Niccolò Righetti, Yingda Dong","doi":"10.1109/IMW56887.2023.10145969","DOIUrl":null,"url":null,"abstract":"In this work, we present the first electrical characterization and modeling of the impact on long-term data retention of distributed cycling in charge trap (CT) 3D NAND arrays. Dependence on Program/Erase cycling conditions of trapassisted tunneling (TAT), charge detrapping, and lateral charge migration (LCM) are experimentally evaluated and modeled. It is demonstrated that post-cycling TAT degradation depends only on the overall cycling dose and not on cycling temperature nor on the delays in-between each Program/Erase operation. On the other hand, charge detrapping follows the same time and temperature dynamics as the ones observed in floating-gate NAND arrays. Finally, LCM is observed to improve with increasing cycling dose and cycling temperature but to be negligibly dependent on the cycling duration. Results are a cornerstone in designing accelerated cycling tests for CT 3D NAND arrays qualification.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Distributed Cycling in Charge Trap-Based 3D NAND Arrays: Model and Qualification Tests Implications\",\"authors\":\"G. Nicosia, Niccolò Righetti, Yingda Dong\",\"doi\":\"10.1109/IMW56887.2023.10145969\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we present the first electrical characterization and modeling of the impact on long-term data retention of distributed cycling in charge trap (CT) 3D NAND arrays. Dependence on Program/Erase cycling conditions of trapassisted tunneling (TAT), charge detrapping, and lateral charge migration (LCM) are experimentally evaluated and modeled. It is demonstrated that post-cycling TAT degradation depends only on the overall cycling dose and not on cycling temperature nor on the delays in-between each Program/Erase operation. On the other hand, charge detrapping follows the same time and temperature dynamics as the ones observed in floating-gate NAND arrays. Finally, LCM is observed to improve with increasing cycling dose and cycling temperature but to be negligibly dependent on the cycling duration. Results are a cornerstone in designing accelerated cycling tests for CT 3D NAND arrays qualification.\",\"PeriodicalId\":153429,\"journal\":{\"name\":\"2023 IEEE International Memory Workshop (IMW)\",\"volume\":\"99 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE International Memory Workshop (IMW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMW56887.2023.10145969\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW56887.2023.10145969","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
在这项工作中,我们首次提出了电荷阱(CT) 3D NAND阵列中分布式循环对长期数据保留影响的电学表征和建模。对陷阱辅助隧道(TAT)、电荷脱陷和侧向电荷迁移(LCM)的依赖程序/擦除循环条件进行了实验评估和建模。结果表明,循环后的TAT降解仅取决于总循环剂量,而不取决于循环温度,也不取决于每次Program/Erase操作之间的延迟。另一方面,电荷脱陷遵循与在浮动门NAND阵列中观察到的相同的时间和温度动力学。最后,观察到LCM随循环剂量和循环温度的增加而改善,但与循环时间的相关性可以忽略不计。结果是设计CT 3D NAND阵列认证加速循环测试的基石。
Distributed Cycling in Charge Trap-Based 3D NAND Arrays: Model and Qualification Tests Implications
In this work, we present the first electrical characterization and modeling of the impact on long-term data retention of distributed cycling in charge trap (CT) 3D NAND arrays. Dependence on Program/Erase cycling conditions of trapassisted tunneling (TAT), charge detrapping, and lateral charge migration (LCM) are experimentally evaluated and modeled. It is demonstrated that post-cycling TAT degradation depends only on the overall cycling dose and not on cycling temperature nor on the delays in-between each Program/Erase operation. On the other hand, charge detrapping follows the same time and temperature dynamics as the ones observed in floating-gate NAND arrays. Finally, LCM is observed to improve with increasing cycling dose and cycling temperature but to be negligibly dependent on the cycling duration. Results are a cornerstone in designing accelerated cycling tests for CT 3D NAND arrays qualification.