{"title":"数字计算机和容错系统故障行为的表征","authors":"S. Bavuso, P. Miner","doi":"10.1109/HICSS.1989.47155","DOIUrl":null,"url":null,"abstract":"Research that is being conducted to characterize the latent fault in digital fault-tolerant systems is addressed. A series of investigations that have led to the development of a practical high-speed gate-level logic simulator is described. The validation of the high-speed simulator, using faultable software, and hardware simulations of a prototype MIS-STD-1750A processor are discussed.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"101 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Characterization of the faulted behavior of digital computers and fault tolerant systems\",\"authors\":\"S. Bavuso, P. Miner\",\"doi\":\"10.1109/HICSS.1989.47155\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Research that is being conducted to characterize the latent fault in digital fault-tolerant systems is addressed. A series of investigations that have led to the development of a practical high-speed gate-level logic simulator is described. The validation of the high-speed simulator, using faultable software, and hardware simulations of a prototype MIS-STD-1750A processor are discussed.<<ETX>>\",\"PeriodicalId\":300182,\"journal\":{\"name\":\"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track\",\"volume\":\"101 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-01-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HICSS.1989.47155\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HICSS.1989.47155","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characterization of the faulted behavior of digital computers and fault tolerant systems
Research that is being conducted to characterize the latent fault in digital fault-tolerant systems is addressed. A series of investigations that have led to the development of a practical high-speed gate-level logic simulator is described. The validation of the high-speed simulator, using faultable software, and hardware simulations of a prototype MIS-STD-1750A processor are discussed.<>
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