H. Kyuragi, S. Konaka, T. Kobayashi, K. Deguchi, E. Yamamoto, S. Ohki, Y. Yamamoto
{"title":"深亚半微米BiCMOS同步x射线光刻技术及其在58ps 2v CMOS门阵列上的应用","authors":"H. Kyuragi, S. Konaka, T. Kobayashi, K. Deguchi, E. Yamamoto, S. Ohki, Y. Yamamoto","doi":"10.1109/VLSIT.1992.200627","DOIUrl":null,"url":null,"abstract":"Deep sub-half-micron BiCMOS technology using synchrotron X-ray lithography and two-level metallization featuring planarization and selective CVD Al plugs is described. The process achieves a 0.24- mu m-wide first wiring resist pattern and contact resistivity of 5*10/sup -10/ Omega -cm/sup 2/ for a 0.25- mu m via hole. A 4 K-gate 0.25- mu m CMOS gate array LSI that operates at 58 ps/gate at 2 V was fabricated. This result demonstrates the efficacy of synchrotron X-ray lithography in the fabrication of sub-quarter-micron BiCMOS ULSIs.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Deep subhalf-micron BiCMOS technology using synchrotron X-ray lithography and its application to 58 ps 2 V CMOS gate array\",\"authors\":\"H. Kyuragi, S. Konaka, T. Kobayashi, K. Deguchi, E. Yamamoto, S. Ohki, Y. Yamamoto\",\"doi\":\"10.1109/VLSIT.1992.200627\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Deep sub-half-micron BiCMOS technology using synchrotron X-ray lithography and two-level metallization featuring planarization and selective CVD Al plugs is described. The process achieves a 0.24- mu m-wide first wiring resist pattern and contact resistivity of 5*10/sup -10/ Omega -cm/sup 2/ for a 0.25- mu m via hole. A 4 K-gate 0.25- mu m CMOS gate array LSI that operates at 58 ps/gate at 2 V was fabricated. This result demonstrates the efficacy of synchrotron X-ray lithography in the fabrication of sub-quarter-micron BiCMOS ULSIs.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200627\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200627","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Deep subhalf-micron BiCMOS technology using synchrotron X-ray lithography and its application to 58 ps 2 V CMOS gate array
Deep sub-half-micron BiCMOS technology using synchrotron X-ray lithography and two-level metallization featuring planarization and selective CVD Al plugs is described. The process achieves a 0.24- mu m-wide first wiring resist pattern and contact resistivity of 5*10/sup -10/ Omega -cm/sup 2/ for a 0.25- mu m via hole. A 4 K-gate 0.25- mu m CMOS gate array LSI that operates at 58 ps/gate at 2 V was fabricated. This result demonstrates the efficacy of synchrotron X-ray lithography in the fabrication of sub-quarter-micron BiCMOS ULSIs.<>
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