Internally matched microwave broadband linear power FET

IN MICROWAVE circuit applications of high power GaAs FETs with as much as 1-W output, matching limitations for lowimpedance devices, resulting from fixed parasitic elements in mounting and packaging of device chips, are serious problems. To solve such matching limitations and achieve broadband power amplification, the introduction of internal matching networks seems effective. This paper will describe broadband internal matching developed for high-power GaAs MESFETs at C-band, adopting both small-signal and large-signal characterizations in the circuit design. The internally matched FET that has been developed is 4.5 mm in length, has a 1-W power output at 1-dB gain compression and a 1.8-W saturated power output with a linear gain of 6.5 dB from 4.6 to 7.6 GHz, without external matching. The FET has a two-cell single-chip structure which has 56 parallel-gates with four bonding pads, and four drain pads. The gate length is 1.3 p m and the total gate width is 5600 pm. To reduce bonding wire inductance for source grounding, the source electrode is grounded by metal thin films evaporated on the device periphery without bonding wires. An input-matching network of the lumped-element twosection low-pass type and an output-matching network of one-section semidistributed form were designed, as shown in Figure 1. For broadband power amplification, the design of the input and output networks was based on the use of measured small-signal S-parameters of the FET chip. Initial values for the input network elements were determined by defining a Chebyshev impedance-matching network of lowpass filter form, after canceling an input reactance with a series inductance at 6 GHz. Then, based on the initial circuit element values and the S-parameters, detailed fitting was performed by computer simulation. In this process of simulation, especially for the output network, to achieve broadband high-power saturation, large-signal matching was attempted by considering the increase of the optimum load conductance of the FET with the increase of input power drive level. With an equivalent load-pull characterization method’ developed in the laboratory, large-signal power-load characteristics of the FET with the internal matching networks were measured. It was confirmed, as shown in Figure 3, that the optimum load for power output approaches 5 0 o h m with the increase of input power level. In the figure, the bullets show small-signal output impedances and triangler/squares indicate optimum power load impedances in large-signal operation. Now, the small-signal optimum load impedance is the complex