{"title":"比较CMOS体和FinFET技术中的高性能电池","authors":"C. Meinhardt, R. Reis","doi":"10.1109/LASCAS.2014.6820310","DOIUrl":null,"url":null,"abstract":"Technology evolution brings new challenges to integrated circuits (IC) design. Parameter variation and complex design rules demand a great effort to create suitable design approaches to ensure manufacturability. Regular layout techniques allow a more accurate estimate of the circuit power and delay in early design steps. In this context, this work presents an evaluation of a set of basic cells candidates to integrate a 32nm high performance cell library in a regular layout synthesis flow. Considering a delay optimization flow, Inverters, NAND2 and NOR2 gates in CMOS bulk technology have shown better dynamic and static power results, when compared with predictive FinFET technologies.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Comparing high-performance cells in CMOS bulk and FinFET technologies\",\"authors\":\"C. Meinhardt, R. Reis\",\"doi\":\"10.1109/LASCAS.2014.6820310\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Technology evolution brings new challenges to integrated circuits (IC) design. Parameter variation and complex design rules demand a great effort to create suitable design approaches to ensure manufacturability. Regular layout techniques allow a more accurate estimate of the circuit power and delay in early design steps. In this context, this work presents an evaluation of a set of basic cells candidates to integrate a 32nm high performance cell library in a regular layout synthesis flow. Considering a delay optimization flow, Inverters, NAND2 and NOR2 gates in CMOS bulk technology have shown better dynamic and static power results, when compared with predictive FinFET technologies.\",\"PeriodicalId\":235336,\"journal\":{\"name\":\"2014 IEEE 5th Latin American Symposium on Circuits and Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE 5th Latin American Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LASCAS.2014.6820310\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2014.6820310","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Comparing high-performance cells in CMOS bulk and FinFET technologies
Technology evolution brings new challenges to integrated circuits (IC) design. Parameter variation and complex design rules demand a great effort to create suitable design approaches to ensure manufacturability. Regular layout techniques allow a more accurate estimate of the circuit power and delay in early design steps. In this context, this work presents an evaluation of a set of basic cells candidates to integrate a 32nm high performance cell library in a regular layout synthesis flow. Considering a delay optimization flow, Inverters, NAND2 and NOR2 gates in CMOS bulk technology have shown better dynamic and static power results, when compared with predictive FinFET technologies.