高速低功耗多端口sram的电路技术

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI:10.1109/ASIC.1998.722823

M. Khellah, M. Elmasry

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引用次数: 8

摘要

本文提出了一种基于电流模式的多端口sram降低功耗、提高读写速度的新方法。本文描述了利用上述技术实现的32/spl times/64寄存器文件的流水线设计。在0.6 /spl mu/m CMOS技术下的仿真结果表明，该寄存器文件可以使用2.3 V电源在500mhz频率下工作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Circuit techniques for high-speed and low-power multi-port SRAMs

This paper presents a new approach based on current-mode to reduce the energy and improve the speed of write and read accesses in multi-port SRAMs. The design of a pipelined 32/spl times/64 register file that utilizes the above technique is described. Simulation results in a 0.6 /spl mu/m CMOS technology show that the register file can operate at a 500 MHz frequency using a 2.3 V supply.

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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

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