弥合测试速度差距:延迟可测试性设计

Proceedings IEEE European Test Workshop Pub Date : 2000-05-23 DOI:10.1109/ETW.2000.873771

H. Speek, H. Kerkhoff, M. Sachdev, M. Shashaani

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引用次数: 8

摘要

高速数字集成电路的经济测试正变得越来越成问题。由于这些ic的高速限制，即使是先进、昂贵的测试器也并不总是能够测试这些ic。本文的重点是设计一种延迟可测试性技术，使高速ic可以使用廉价的低速ATE进行测试。此外，还讨论了可能的完全BIST延迟故障的扩展。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Bridging the testing speed gap: design for delay testability

The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed.

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Proceedings IEEE European Test Workshop

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