采用基于电流的参考方案的16kb 1T1C FeRAM测试芯片

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012777

J. Siu, Y. Eslami, A. Sheikholeslami, P. Gulak, T. Endo, S. Kawashima

{"title":"采用基于电流的参考方案的16kb 1T1C FeRAM测试芯片","authors":"J. Siu, Y. Eslami, A. Sheikholeslami, P. Gulak, T. Endo, S. Kawashima","doi":"10.1109/CICC.2002.1012777","DOIUrl":null,"url":null,"abstract":"A 16 kb 1T1C FeRAM test chip is designed and fabricated in a 0.35 /spl mu/m FeRAM process. The test chip uses a reference generation scheme that balances fatigue evenly between memory cells and reference cells, hence providing the 1T1C cell with 2T2C robustness to fatigue. The test chip achieves an access time of 62 ns at 3V.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 16 kb 1T1C FeRAM test chip using current-based reference scheme\",\"authors\":\"J. Siu, Y. Eslami, A. Sheikholeslami, P. Gulak, T. Endo, S. Kawashima\",\"doi\":\"10.1109/CICC.2002.1012777\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 16 kb 1T1C FeRAM test chip is designed and fabricated in a 0.35 /spl mu/m FeRAM process. The test chip uses a reference generation scheme that balances fatigue evenly between memory cells and reference cells, hence providing the 1T1C cell with 2T2C robustness to fatigue. The test chip achieves an access time of 62 ns at 3V.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012777\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012777","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

以0.35 /spl mu/m的FeRAM工艺设计并制作了一个16kb的1T1C FeRAM测试芯片。测试芯片采用参考生成方案，在记忆单元和参考单元之间均匀平衡疲劳，从而为1T1C单元提供2T2C抗疲劳的鲁棒性。测试芯片在3V下实现了62 ns的访问时间。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A 16 kb 1T1C FeRAM test chip using current-based reference scheme

A 16 kb 1T1C FeRAM test chip is designed and fabricated in a 0.35 /spl mu/m FeRAM process. The test chip uses a reference generation scheme that balances fatigue evenly between memory cells and reference cells, hence providing the 1T1C cell with 2T2C robustness to fatigue. The test chip achieves an access time of 62 ns at 3V.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

自引率

0.00%

发文量