有限域GF(2/sup m/)上串行乘法的新结构

M.C. Mekhallalati, A. Ashur
{"title":"有限域GF(2/sup m/)上串行乘法的新结构","authors":"M.C. Mekhallalati, A. Ashur","doi":"10.1109/VLSISP.1996.558302","DOIUrl":null,"url":null,"abstract":"Two novel uni-directional systolic structures for serial multiplication over the finite field GF(2/sup m/) are presented. The architecture of the new structures posses features of regularity, modularity, and uni-directional data flow. One of the new structures is a serial-parallel structure, whereas the other structure is a fully serial one. Both structures consist of (m/2) novel cells. Due to the novel cells architectures of the new structures, the initial delay (i.e. the number of cycles required to obtain the first output) and the latency (i.e. the number of cycles required to complete the multiplication process) are decreased by 25% and 17% respectively. Also, the number of latches of the new structures are reduced by more than 20% when compared to existing uni-directional serial-parallel structures.","PeriodicalId":290885,"journal":{"name":"VLSI Signal Processing, IX","volume":"163 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Novel structures for serial multiplication over the finite field GF(2/sup m/)\",\"authors\":\"M.C. Mekhallalati, A. Ashur\",\"doi\":\"10.1109/VLSISP.1996.558302\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Two novel uni-directional systolic structures for serial multiplication over the finite field GF(2/sup m/) are presented. The architecture of the new structures posses features of regularity, modularity, and uni-directional data flow. One of the new structures is a serial-parallel structure, whereas the other structure is a fully serial one. Both structures consist of (m/2) novel cells. Due to the novel cells architectures of the new structures, the initial delay (i.e. the number of cycles required to obtain the first output) and the latency (i.e. the number of cycles required to complete the multiplication process) are decreased by 25% and 17% respectively. Also, the number of latches of the new structures are reduced by more than 20% when compared to existing uni-directional serial-parallel structures.\",\"PeriodicalId\":290885,\"journal\":{\"name\":\"VLSI Signal Processing, IX\",\"volume\":\"163 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI Signal Processing, IX\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSISP.1996.558302\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Signal Processing, IX","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSISP.1996.558302","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

在有限域GF(2/sup m/)上提出了两种新的单向收缩结构。新结构的体系结构具有规律性、模块化和单向数据流的特点。其中一种结构是串并联结构,另一种结构是全串联结构。这两种结构都由(m/2)个新细胞组成。由于新结构的新颖单元结构,初始延迟(即获得第一个输出所需的循环次数)和延迟(即完成乘法过程所需的循环次数)分别降低了25%和17%。此外,与现有的单向串并联结构相比,新结构的锁存器数量减少了20%以上。
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Novel structures for serial multiplication over the finite field GF(2/sup m/)
Two novel uni-directional systolic structures for serial multiplication over the finite field GF(2/sup m/) are presented. The architecture of the new structures posses features of regularity, modularity, and uni-directional data flow. One of the new structures is a serial-parallel structure, whereas the other structure is a fully serial one. Both structures consist of (m/2) novel cells. Due to the novel cells architectures of the new structures, the initial delay (i.e. the number of cycles required to obtain the first output) and the latency (i.e. the number of cycles required to complete the multiplication process) are decreased by 25% and 17% respectively. Also, the number of latches of the new structures are reduced by more than 20% when compared to existing uni-directional serial-parallel structures.
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