M. V. Thayyil, Jan Plíva, Mengqi Cui, N. Joram, F. Ellinger
{"title":"基于22nm FDSOI技术的60ghz低功耗集成准环行器","authors":"M. V. Thayyil, Jan Plíva, Mengqi Cui, N. Joram, F. Ellinger","doi":"10.1109/SiRF51851.2021.9383419","DOIUrl":null,"url":null,"abstract":"This work presents the design and characterization of a millimeter wave integrated quasi-circulator implemented in a 22 nm fully depleted silicon on insulator technology, targeting single antenna radio frequency identification systems. The design is based on a Wilkinson power divider and a common-gate loss compensation amplifier. Characterization results show that all ports are matched to 50Ω with magnitude of input reflection coefficients better than -10 dB. The measured transmit port to antenna port insertion loss is 5.7 dB, and the antenna port to receive port gain is 2 dB. The power amplifier port to loss compensation amplifier isolation is greater than 20 dB in the 57 GHz to 63 GHz frequency range, with a maximum of 32 dB. The circuit consumes 5.4mW power and occupies an area of 0.49 mm2. To the knowledge of the authors, the design has one of the best reported combinations of isolation, power consumption and occupied area among integrated quasi-circulators.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 60 GHz Low Power Integrated Quasi-Circulator in 22 nm FDSOI Technology\",\"authors\":\"M. V. Thayyil, Jan Plíva, Mengqi Cui, N. Joram, F. Ellinger\",\"doi\":\"10.1109/SiRF51851.2021.9383419\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents the design and characterization of a millimeter wave integrated quasi-circulator implemented in a 22 nm fully depleted silicon on insulator technology, targeting single antenna radio frequency identification systems. The design is based on a Wilkinson power divider and a common-gate loss compensation amplifier. Characterization results show that all ports are matched to 50Ω with magnitude of input reflection coefficients better than -10 dB. The measured transmit port to antenna port insertion loss is 5.7 dB, and the antenna port to receive port gain is 2 dB. The power amplifier port to loss compensation amplifier isolation is greater than 20 dB in the 57 GHz to 63 GHz frequency range, with a maximum of 32 dB. The circuit consumes 5.4mW power and occupies an area of 0.49 mm2. To the knowledge of the authors, the design has one of the best reported combinations of isolation, power consumption and occupied area among integrated quasi-circulators.\",\"PeriodicalId\":166842,\"journal\":{\"name\":\"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-01-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SiRF51851.2021.9383419\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SiRF51851.2021.9383419","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 60 GHz Low Power Integrated Quasi-Circulator in 22 nm FDSOI Technology
This work presents the design and characterization of a millimeter wave integrated quasi-circulator implemented in a 22 nm fully depleted silicon on insulator technology, targeting single antenna radio frequency identification systems. The design is based on a Wilkinson power divider and a common-gate loss compensation amplifier. Characterization results show that all ports are matched to 50Ω with magnitude of input reflection coefficients better than -10 dB. The measured transmit port to antenna port insertion loss is 5.7 dB, and the antenna port to receive port gain is 2 dB. The power amplifier port to loss compensation amplifier isolation is greater than 20 dB in the 57 GHz to 63 GHz frequency range, with a maximum of 32 dB. The circuit consumes 5.4mW power and occupies an area of 0.49 mm2. To the knowledge of the authors, the design has one of the best reported combinations of isolation, power consumption and occupied area among integrated quasi-circulators.