基于22nm FDSOI技术的60ghz低功耗集成准环行器

M. V. Thayyil, Jan Plíva, Mengqi Cui, N. Joram, F. Ellinger
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引用次数: 0

摘要

这项工作提出了一种毫米波集成准环行器的设计和特性,该环行器采用22纳米全耗尽硅绝缘体技术实现,针对单天线射频识别系统。该设计基于威尔金森功率分配器和共门损耗补偿放大器。表征结果表明,所有端口都与50Ω匹配,输入反射系数的幅度大于-10 dB。测得发射端口到天线端口的插入损耗为5.7 dB,天线端口到接收端口的增益为2db。在57ghz ~ 63ghz频率范围内,功率放大器端口对损耗补偿放大器的隔离度大于20db,最大隔离度为32db。电路功耗为5.4mW,占地面积为0.49 mm2。据作者所知,该设计在集成准环行器中具有隔离、功耗和占用面积的最佳组合之一。
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A 60 GHz Low Power Integrated Quasi-Circulator in 22 nm FDSOI Technology
This work presents the design and characterization of a millimeter wave integrated quasi-circulator implemented in a 22 nm fully depleted silicon on insulator technology, targeting single antenna radio frequency identification systems. The design is based on a Wilkinson power divider and a common-gate loss compensation amplifier. Characterization results show that all ports are matched to 50Ω with magnitude of input reflection coefficients better than -10 dB. The measured transmit port to antenna port insertion loss is 5.7 dB, and the antenna port to receive port gain is 2 dB. The power amplifier port to loss compensation amplifier isolation is greater than 20 dB in the 57 GHz to 63 GHz frequency range, with a maximum of 32 dB. The circuit consumes 5.4mW power and occupies an area of 0.49 mm2. To the knowledge of the authors, the design has one of the best reported combinations of isolation, power consumption and occupied area among integrated quasi-circulators.
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