Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383331
Xuewei Ding, G. Niu, Anni Zhang, W. Cai, K. Imura
This paper experimentally extracts the extrinsic and intrinsic thermal noise γ factors in a 14-nm FinFET technology. The intrinsic γ in saturation operation is found to be close to 1 for the minimum L (16nm) transistors, which is surprisingly low compared to the long channel limit of 2/3. We attribute this low noise factor to the excellent gate control of these FinFETs that makes the transistor exhibit relatively long channel thermal noise behavior at minimum gate length.
{"title":"Experimental Extraction of Thermal Noise γ Factors in a 14-nm RF FinFET technology","authors":"Xuewei Ding, G. Niu, Anni Zhang, W. Cai, K. Imura","doi":"10.1109/SiRF51851.2021.9383331","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383331","url":null,"abstract":"This paper experimentally extracts the extrinsic and intrinsic thermal noise γ factors in a 14-nm FinFET technology. The intrinsic γ in saturation operation is found to be close to 1 for the minimum L (16nm) transistors, which is surprisingly low compared to the long channel limit of 2/3. We attribute this low noise factor to the excellent gate control of these FinFETs that makes the transistor exhibit relatively long channel thermal noise behavior at minimum gate length.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123598559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383408
Andrea Ashley, G. Lasser, Z. Popovic, A. Madanayake, D. Psychogiou
This paper discusses the RF design and characterization of an X-band MMIC isolator. It is based on a directional coupler and a non-reciprocal RF signal path that comprises a gain stage and two transmission line elements for phase control. In this manner, enhanced power transmission is obtained in the forward direction and isolation in the reverse one. The operating principles and RF design trade-offs (isolation, gain, matching) of the isolator are presented through circuit-based analysis. For proof-of-concept demonstration purposes, a prototype was designed at X-band and manufactured with a commercial MMIC GaAs process. Its RF measured performance is summarized as follows: center frequency: 9.4 GHz, maximum gain = 9.3 dB, maximum isolation = 27.7 dB, and 3 dB passband bandwidth with > 23 dB of isolation= 1.61 GHz.
{"title":"MMIC GaAs X-Band Isolator with Enhanced Power Transmission Response","authors":"Andrea Ashley, G. Lasser, Z. Popovic, A. Madanayake, D. Psychogiou","doi":"10.1109/SiRF51851.2021.9383408","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383408","url":null,"abstract":"This paper discusses the RF design and characterization of an X-band MMIC isolator. It is based on a directional coupler and a non-reciprocal RF signal path that comprises a gain stage and two transmission line elements for phase control. In this manner, enhanced power transmission is obtained in the forward direction and isolation in the reverse one. The operating principles and RF design trade-offs (isolation, gain, matching) of the isolator are presented through circuit-based analysis. For proof-of-concept demonstration purposes, a prototype was designed at X-band and manufactured with a commercial MMIC GaAs process. Its RF measured performance is summarized as follows: center frequency: 9.4 GHz, maximum gain = 9.3 dB, maximum isolation = 27.7 dB, and 3 dB passband bandwidth with > 23 dB of isolation= 1.61 GHz.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"476 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116688493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383346
R. Ciocoveanu, V. Issakov
This paper presents a highly-integrated low-power 57 − 64 GHz receiver realized in a 28 nm bulk CMOS technology. The receiver chip integrates RF front-end and analog baseband (ABB), designed specifically for short-range frequency-modulated continuous wave (FMCW) radar systems. The RF front-end includes an LNA, a passive mixer and a transimpedance amplifier (TIA), while the analog signal processing chain consists of an active high-pass-filter (HPF), programmable gain amplifier (PGA) and 4th order anti-aliasing filter (AAF). To enhance the temperature stability, constant gm biasing is implemented. Furthermore, DTMOS technique is used to make biasing more robust against PVT variations. The receiver achieves peak conversion gain of 77 dB and overall noise figure of 13 dB, with the ABB contribution. The chip including pads occupies an area of only 700 μm × 625 μm. The circuit is operated from a single 0.9 V supply and draws 44 mA for the RF front-end and 2.2 mA for the ABB chain, resulting in 42 mW.
{"title":"Low-Power 60GHz Receiver with an Integrated Analog Baseband for FMCW Radar Applications in 28nm CMOS Technology","authors":"R. Ciocoveanu, V. Issakov","doi":"10.1109/SiRF51851.2021.9383346","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383346","url":null,"abstract":"This paper presents a highly-integrated low-power 57 − 64 GHz receiver realized in a 28 nm bulk CMOS technology. The receiver chip integrates RF front-end and analog baseband (ABB), designed specifically for short-range frequency-modulated continuous wave (FMCW) radar systems. The RF front-end includes an LNA, a passive mixer and a transimpedance amplifier (TIA), while the analog signal processing chain consists of an active high-pass-filter (HPF), programmable gain amplifier (PGA) and 4th order anti-aliasing filter (AAF). To enhance the temperature stability, constant gm biasing is implemented. Furthermore, DTMOS technique is used to make biasing more robust against PVT variations. The receiver achieves peak conversion gain of 77 dB and overall noise figure of 13 dB, with the ABB contribution. The chip including pads occupies an area of only 700 μm × 625 μm. The circuit is operated from a single 0.9 V supply and draws 44 mA for the RF front-end and 2.2 mA for the ABB chain, resulting in 42 mW.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114478132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383400
G. Dziallas, A. Fatemi, A. Malignaggi, G. Kahmen
In this paper we present a broadband low-noise monolithic-integrated silicon photonic receiver with automatic gain control that shows state-of-the-art performance. The electronic and photonic components are fabricated monolithically on one chip using IHP’s 0.25μm SiGe BiCMOS EPIC technology. The optical receiver features a high tunable transimpedance gain of 66 dBW at a large opto-electrical BW of 34 GHz and an input-referred noise current of 2.81 μArms while consuming 205 mW of power. Comparing key performance metrics and the functional complexity of similar devices found in the literature, the optical receiver presented in this work achieves an overall superior performance.
{"title":"A Monolithic-Integrated Broadband Low-Noise Optical Receiver with Automatic Gain Control in 0.25μm SiGe BiCMOS","authors":"G. Dziallas, A. Fatemi, A. Malignaggi, G. Kahmen","doi":"10.1109/SiRF51851.2021.9383400","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383400","url":null,"abstract":"In this paper we present a broadband low-noise monolithic-integrated silicon photonic receiver with automatic gain control that shows state-of-the-art performance. The electronic and photonic components are fabricated monolithically on one chip using IHP’s 0.25μm SiGe BiCMOS EPIC technology. The optical receiver features a high tunable transimpedance gain of 66 dBW at a large opto-electrical BW of 34 GHz and an input-referred noise current of 2.81 μArms while consuming 205 mW of power. Comparing key performance metrics and the functional complexity of similar devices found in the literature, the optical receiver presented in this work achieves an overall superior performance.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133532916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383332
Badou Sene, H. Knapp, Daniel Reiter, N. Pohl
A novel monostatic transceiver topology that makes use of a diode-based mixer and operates from 143.8 to 158.1 GHz is proposed. The architecture avoids using couplers and the associated limitations. Hence, it allows to save space and minimizes losses. The signal travels directly from the VCO to the antenna through a diode-connected npn transistor, which performs the mixing. For the transmitted signal, solely a small insertion loss of less than 1.8 dB occurs. The complete mixer circuit only consumes an area of 65 x 260 µm2. Furthermore, the transceiver concept significantly improves the signal-to-noise ratio.
提出了一种新的单稳态收发器拓扑，该拓扑利用基于二极管的混频器，工作频率为143.8至158.1 GHz。该体系结构避免使用耦合器和相关的限制。因此，它可以节省空间并最大限度地减少损失。信号直接从VCO通过一个二极管连接的npn晶体管传播到天线，该晶体管执行混合。对于传输的信号，只有小于1.8 dB的小插入损耗。整个混频器电路仅消耗65 x 260µm2的面积。此外，收发器的概念显著提高了信噪比。
{"title":"A Compact Monostatic Transceiver Topology Using a Diode-Based Mixer","authors":"Badou Sene, H. Knapp, Daniel Reiter, N. Pohl","doi":"10.1109/SiRF51851.2021.9383332","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383332","url":null,"abstract":"A novel monostatic transceiver topology that makes use of a diode-based mixer and operates from 143.8 to 158.1 GHz is proposed. The architecture avoids using couplers and the associated limitations. Hence, it allows to save space and minimizes losses. The signal travels directly from the VCO to the antenna through a diode-connected npn transistor, which performs the mixing. For the transmitted signal, solely a small insertion loss of less than 1.8 dB occurs. The complete mixer circuit only consumes an area of 65 x 260 µm2. Furthermore, the transceiver concept significantly improves the signal-to-noise ratio.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116515242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383328
Sascha Breun, Albert-Marcel Schrotz, M. Dietz, V. Issakov, R. Weigel
This paper presents a 314-344 GHz high output power push-push frequency doubler for radar applications with 1 dBm Psat at 324 GHz and 30 GHz Psat 3 dB–bandwidth. It is driven by a three-stage, cascode-based D-band driving stage, providing a differential saturated output power of 14.3 dBm at 154 GHz with a peak PAE of 4.5% and 13.4 dBm output referred P1 dB. The chip is fabricated using a 130 nm SiGe BiCMOS technology with ft/fmax of 250 GHz / 370 GHz. Thanks to the use of harmonic reflectors an overall peak conversion gain of 20 dB is achieved and remains above 6 dB at saturation.
{"title":"A 314-344 GHz Frequency Doubler with Driving Stage and 1 dBm Psat in SiGe BiCMOS Technology","authors":"Sascha Breun, Albert-Marcel Schrotz, M. Dietz, V. Issakov, R. Weigel","doi":"10.1109/SiRF51851.2021.9383328","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383328","url":null,"abstract":"This paper presents a 314-344 GHz high output power push-push frequency doubler for radar applications with 1 dBm Psat at 324 GHz and 30 GHz Psat 3 dB–bandwidth. It is driven by a three-stage, cascode-based D-band driving stage, providing a differential saturated output power of 14.3 dBm at 154 GHz with a peak PAE of 4.5% and 13.4 dBm output referred P1 dB. The chip is fabricated using a 130 nm SiGe BiCMOS technology with ft/fmax of 250 GHz / 370 GHz. Thanks to the use of harmonic reflectors an overall peak conversion gain of 20 dB is achieved and remains above 6 dB at saturation.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130316788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383343
G. Park, Jae Kwang Kwon, D. Kang, C. Park
A 60-GHz variable-gain amplifier with a phase-compensated variable attenuator is proposed herein. The proposed circuit comprises a four-stage common-source amplifier and a phase-compensated attenuator. The proposed circuit is implemented using a 65-nm CMOS process and occupies 360 μm × 765 μm including pads. The measured peak gain is 15.2 dB, and the 3-dB bandwidth exceeds 17.5 GHz from 49.5 to over 67 GHz. In addition, the proposed circuit achieves a gain control range exceeding 14.7 dB within a 3-dB bandwidth. Owing to the proposed phase compensation technique, the phase-compensated attenuator exhibits a maximum phase error of 2.9° and a RMS phase error of 1.7° at 56 GHz while consuming only 11.8 mW of DC power.
{"title":"A 60-GHz Variable Gain Amplifier with Phase-compensated Variable Attenuator","authors":"G. Park, Jae Kwang Kwon, D. Kang, C. Park","doi":"10.1109/SiRF51851.2021.9383343","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383343","url":null,"abstract":"A 60-GHz variable-gain amplifier with a phase-compensated variable attenuator is proposed herein. The proposed circuit comprises a four-stage common-source amplifier and a phase-compensated attenuator. The proposed circuit is implemented using a 65-nm CMOS process and occupies 360 μm × 765 μm including pads. The measured peak gain is 15.2 dB, and the 3-dB bandwidth exceeds 17.5 GHz from 49.5 to over 67 GHz. In addition, the proposed circuit achieves a gain control range exceeding 14.7 dB within a 3-dB bandwidth. Owing to the proposed phase compensation technique, the phase-compensated attenuator exhibits a maximum phase error of 2.9° and a RMS phase error of 1.7° at 56 GHz while consuming only 11.8 mW of DC power.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115276092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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