Over GHz low-power RF clock distribution for a multiprocessor digital system

Conventional digital clock distribution interconnection causes a severe power consumption problem for GHz clock distribution because of transmission line losses, and it exhibits difficult signal integrity problems due to clock skew, clock jitter and signal reflection. To overcome these conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, especially multi-processor systems using global clocking. In this paper, we firstly report signal integrity analysis including power, skew, jitter, crosstalk, reflection, and noise in the RF clock distribution system. Based on this analysis, we propose a novel signal integrity design methodology for the RF clock distribution. The system comprises an RF clock transmitter as a clock generator, an H clock tree with junction couplers as a clock distributing network and an RF receiver as a digital clock-recovering module. We assume solder-ball flip chip interconnects for the chip-to-substrate assembly and 0.35 /spl mu/m TSMC CMOS technology for the RF clock receiver. The clock skew and the clock jitter created by process parameter variations or modeled and predicted. Finally, we demonstrate the RCD as a low-power and high-performance clocking method using HP Advanced Design System (ADS) simulation considering the microwave frequency interconnection models and the process parameter variations.