{"title":"基于FPGA的国际象棋走法生成器","authors":"M. Boule, Z. Zilic","doi":"10.1109/CICC.2002.1012769","DOIUrl":null,"url":null,"abstract":"This paper details the architecture of an FPGA chess-move generator. The design is based on Deep Blue's move generator. The inherent differences between ASICs and FPGAs imply many design changes. We present improvements that exploit important FPGA features (lookup-table based logic, routing resources, distributed and block RAM).","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"An FPGA based move generator for the game of chess\",\"authors\":\"M. Boule, Z. Zilic\",\"doi\":\"10.1109/CICC.2002.1012769\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper details the architecture of an FPGA chess-move generator. The design is based on Deep Blue's move generator. The inherent differences between ASICs and FPGAs imply many design changes. We present improvements that exploit important FPGA features (lookup-table based logic, routing resources, distributed and block RAM).\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012769\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An FPGA based move generator for the game of chess
This paper details the architecture of an FPGA chess-move generator. The design is based on Deep Blue's move generator. The inherent differences between ASICs and FPGAs imply many design changes. We present improvements that exploit important FPGA features (lookup-table based logic, routing resources, distributed and block RAM).